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Commit 3601d98c authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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arm64: dts: renesas: r8a77980: add [H]SCIF support 



Describe [H]SCIF ports in the R8A77980 device tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: default avatarVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent cfdec2af

arch/arm64/boot/dts/renesas/r8a77980.dtsi

+151 −0
Original line number Diff line number Diff line
@@ -56,6 +56,13 @@ 
		method = "smc";

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;
@@ -85,6 +92,150 @@ 
			#power-domain-cells = <1>;

		};



		hscif0: serial@e6540000 {

			compatible = "renesas,hscif-r8a77980",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6540000 0 0x60>;

			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 520>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x31>, <&dmac1 0x30>,

			       <&dmac2 0x31>, <&dmac2 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 520>;

			status = "disabled";

		};



		hscif1: serial@e6550000 {

			compatible = "renesas,hscif-r8a77980",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6550000 0 0x60>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 519>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x33>, <&dmac1 0x32>,

			       <&dmac2 0x33>, <&dmac2 0x32>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 519>;

			status = "disabled";

		};



		hscif2: serial@e6560000 {

			compatible = "renesas,hscif-r8a77980",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6560000 0 0x60>;

			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 518>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x35>, <&dmac1 0x34>,

			       <&dmac2 0x35>, <&dmac2 0x34>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 518>;

			status = "disabled";

		};



		hscif3: serial@e66a0000 {

			compatible = "renesas,hscif-r8a77980",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe66a0000 0 0x60>;

			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 517>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x37>, <&dmac1 0x36>,

			       <&dmac2 0x37>, <&dmac2 0x36>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 517>;

			status = "disabled";

		};



		scif0: serial@e6e60000 {

			compatible = "renesas,scif-r8a77980",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6e60000 0 0x40>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 207>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,

			       <&dmac2 0x51>, <&dmac2 0x50>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 207>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			compatible = "renesas,scif-r8a77980",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6e68000 0 0x40>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 206>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,

			       <&dmac2 0x53>, <&dmac2 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 206>;

			status = "disabled";

		};



		scif3: serial@e6c50000 {

			compatible = "renesas,scif-r8a77980",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6c50000 0 0x40>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 204>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x57>, <&dmac1 0x56>,

			       <&dmac2 0x57>, <&dmac2 0x56>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 204>;

			status = "disabled";

		};



		scif4: serial@e6c40000 {

			compatible = "renesas,scif-r8a77980",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6c40000 0 0x40>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 203>,

				 <&cpg CPG_CORE 19>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x59>, <&dmac1 0x58>,

			       <&dmac2 0x59>, <&dmac2 0x58>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 203>;

			status = "disabled";

		};



		dmac1: dma-controller@e7300000 {

			compatible = "renesas,dmac-r8a77980",

				     "renesas,rcar-dmac";