Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 35fdd6c9 authored by John Crispin's avatar John Crispin Committed by Matthias Brugger
Browse files

arm: dts: mt7623: add usb nodes to the mt7623.dtsi file 



Add USB nodes to the mt7623.dtsi file.

Signed-off-by: default avatarJohn Crispin <john@phrozen.org>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent ffa491c8

arch/arm/boot/dts/mt7623.dtsi

+77 −0
Original line number Diff line number Diff line
@@ -375,12 +375,89 @@ 
		status = "disabled";

	};



	usb1: usb@1a1c0000 {

		compatible = "mediatek,mt7623-xhci",

			     "mediatek,mt8173-xhci";

		reg = <0 0x1a1c0000 0 0x1000>,

		      <0 0x1a1c4700 0 0x0100>;

		reg-names = "mac", "ippc";

		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,

			 <&topckgen CLK_TOP_ETHIF_SEL>;

		clock-names = "sys_ck", "free_ck";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;

		status = "disabled";

	};



	u3phy1: usb-phy@1a1c4000 {

		compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";

		reg = <0 0x1a1c4000 0 0x0700>;

		clocks = <&clk26m>;

		clock-names = "u3phya_ref";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		status = "disabled";



		u2port0: usb-phy@1a1c4800 {

			reg = <0 0x1a1c4800 0 0x0100>;

			#phy-cells = <1>;

			status = "okay";

		};



		u3port0: usb-phy@1a1c4900 {

			reg = <0 0x1a1c4900 0 0x0700>;

			#phy-cells = <1>;

			status = "okay";

		};

	};



	usb2: usb@1a240000 {

		compatible = "mediatek,mt7623-xhci",

			     "mediatek,mt8173-xhci";

		reg = <0 0x1a240000 0 0x1000>,

		      <0 0x1a244700 0 0x0100>;

		reg-names = "mac", "ippc";

		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,

			 <&topckgen CLK_TOP_ETHIF_SEL>;

		clock-names = "sys_ck", "free_ck";

		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;

		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;

		status = "disabled";

	};



	u3phy2: usb-phy@1a244000 {

		compatible = "mediatek,mt7623-u3phy", "mediatek,mt2701-u3phy";

		reg = <0 0x1a244000 0 0x0700>;

		clocks = <&clk26m>;

		clock-names = "u3phya_ref";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		status = "disabled";



		u2port1: usb-phy@1a244800 {

			reg = <0 0x1a244800 0 0x0100>;

			#phy-cells = <1>;

			status = "okay";

		};



		u3port1: usb-phy@1a244900 {

			reg = <0 0x1a244900 0 0x0700>;

			#phy-cells = <1>;

			status = "okay";

		};

	};



	hifsys: syscon@1a000000 {

		compatible = "mediatek,mt7623-hifsys",

			     "mediatek,mt2701-hifsys",

			     "syscon";

		reg = <0 0x1a000000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	ethsys: syscon@1b000000 {