Merge remote-tracking branches 'spi/topic/fsl-cspi', 'spi/topic/fsl-dspi',...

  (CSPI/eCSPI) for i.MX

Required properties:

- compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi"

- compatible :

  - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1

  - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21

  - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27

  - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31

  - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35

  - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51

- reg : Offset and length of the register set for the device

- interrupts : Should contain CSPI/eCSPI interrupt

- fsl,spi-num-chipselects : Contains the number of the chipselect

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- clocks : Clock specifiers for both ipg and per clocks.

- clock-names : Clock names should include both "ipg" and "per"

See the clock consumer binding,

	Documentation/devicetree/bindings/clock/clock-bindings.txt

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

		Documentation/devicetree/bindings/dma/dma.txt

- dma-names: DMA request names should include "tx" and "rx" if present.

  in big endian mode, otherwise in native mode(same with CPU), for more

  detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.

Optional SPI slave node properties:

- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip

  select and the start of clock signal, at the start of a transfer.

- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock

  signal and deactivating chip select, at the end of a transfer.

Example:

dspi0@4002c000 {

		reg = <0>;

		linux,modalias = "m25p80";

		modal = "at26df081a";

		fsl,spi-cs-sck-delay = <100>;

		fsl,spi-sck-cs-delay = <50>;

	};

};

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/math64.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/sched.h>

#include <linux/spi/spi.h>

#include <linux/spi/spi_bitbang.h>

#include <linux/time.h>

#define DRIVER_NAME "fsl-dspi"

#define SPI_CTAR_CPOL(x)	((x) << 26)

#define SPI_CTAR_CPHA(x)	((x) << 25)

#define SPI_CTAR_LSBFE(x)	((x) << 24)

#define SPI_CTAR_PCSSCR(x)	(((x) & 0x00000003) << 22)

#define SPI_CTAR_PCSSCK(x)	(((x) & 0x00000003) << 22)

#define SPI_CTAR_PASC(x)	(((x) & 0x00000003) << 20)

#define SPI_CTAR_PDT(x)	(((x) & 0x00000003) << 18)

#define SPI_CTAR_PBR(x)	(((x) & 0x00000003) << 16)

#define SPI_CTAR_ASC(x)	(((x) & 0x0000000f) << 8)

#define SPI_CTAR_DT(x)		(((x) & 0x0000000f) << 4)

#define SPI_CTAR_BR(x)		((x) & 0x0000000f)

#define SPI_CTAR_SCALE_BITS	0xf

#define SPI_CTAR0_SLAVE	0x0c

	}

}

static void ns_delay_scale(char *psc, char *sc, int delay_ns,

		unsigned long clkrate)

{

	int pscale_tbl[4] = {1, 3, 5, 7};

	int scale_needed, scale, minscale = INT_MAX;

	int i, j;

	u32 remainder;

	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,

			&remainder);

	if (remainder)

		scale_needed++;

	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)

		for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {

			scale = pscale_tbl[i] * (2 << j);

			if (scale >= scale_needed) {

				if (scale < minscale) {

					minscale = scale;

					*psc = i;

					*sc = j;

				}

				break;

			}

		}

	if (minscale == INT_MAX) {

		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",

			delay_ns, clkrate);

		*psc = ARRAY_SIZE(pscale_tbl) - 1;

		*sc = SPI_CTAR_SCALE_BITS;

	}

}

static int dspi_transfer_write(struct fsl_dspi *dspi)

{

	int tx_count = 0;

{

	struct chip_data *chip;

	struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);

	unsigned char br = 0, pbr = 0, fmsz = 0;

	u32 cs_sck_delay = 0, sck_cs_delay = 0;

	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;

	unsigned char pasc = 0, asc = 0, fmsz = 0;

	unsigned long clkrate;

	if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {

		fmsz = spi->bits_per_word - 1;

			return -ENOMEM;

	}

	of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",

			&cs_sck_delay);

	of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",

			&sck_cs_delay);

	chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |

		SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;

	chip->void_write_data = 0;

	hz_to_spi_baud(&pbr, &br,

			spi->max_speed_hz, clk_get_rate(dspi->clk));

	clkrate = clk_get_rate(dspi->clk);

	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);

	/* Set PCS to SCK delay scale values */

	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);

	/* Set After SCK delay scale values */

	ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);

	chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)

		| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)

		| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)

		| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)

		| SPI_CTAR_PCSSCK(pcssck)

		| SPI_CTAR_CSSCK(cssck)

		| SPI_CTAR_PASC(pasc)

		| SPI_CTAR_ASC(asc)

		| SPI_CTAR_PBR(pbr)

		| SPI_CTAR_BR(br);

	if (tx) {

		desc_tx = dmaengine_prep_slave_sg(master->dma_tx,

					tx->sgl, tx->nents, DMA_TO_DEVICE,

					tx->sgl, tx->nents, DMA_MEM_TO_DEV,

					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc_tx)

			goto no_dma;

	if (rx) {

		desc_rx = dmaengine_prep_slave_sg(master->dma_rx,

					rx->sgl, rx->nents, DMA_FROM_DEVICE,

					rx->sgl, rx->nents, DMA_DEV_TO_MEM,

					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

		if (!desc_rx)

			goto no_dma;

	return mpc512x_psc_spi_do_remove(&op->dev);

}

static struct of_device_id mpc512x_psc_spi_of_match[] = {

static const struct of_device_id mpc512x_psc_spi_of_match[] = {

	{ .compatible = "fsl,mpc5121-psc-spi", },

	{},

};