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Commit 35bcaf00 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
Browse files

ARM: i.MX21 clk: Add devicetree support 



This patch adds devicetree support CCM module for i.MX21 CPUs.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 548694b9

Documentation/devicetree/bindings/clock/imx21-clock.txt

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* Clock bindings for Freescale i.MX21



Required properties:

- compatible  : Should be "fsl,imx21-ccm".

- reg         : Address and length of the register set.

- interrupts  : Should contain CCM interrupt.

- #clock-cells: Should be <1>.



The clock consumer should specify the desired clock by having the clock

ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h

for the full list of i.MX21 clock IDs.



Examples:

	clks: ccm@10027000{

		compatible = "fsl,imx21-ccm";

		reg = <0x10027000 0x800>;

		#clock-cells = <1>;

	};



	uart1: serial@1000a000 {

		compatible = "fsl,imx21-uart";

		reg = <0x1000a000 0x1000>;

		interrupts = <20>;

		clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,

			 <&clks IMX21_CLK_PER1>;

		clock-names = "ipg", "per";

		status = "disabled";

	};

arch/arm/mach-imx/clk-imx21.c

+136 −123
Original line number Original line Diff line number Diff line
@@ -12,149 +12,162 @@ 
#include <linux/clk.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/clk-provider.h>

#include <linux/clkdev.h>

#include <linux/clkdev.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <dt-bindings/clock/imx21-clock.h>





#include "clk.h"

#include "clk.h"

#include "common.h"

#include "common.h"

#include "hardware.h"

#include "hardware.h"





#define IO_ADDR_CCM(off)	(MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))

static void __iomem *ccm __initdata;





/* Register offsets */

/* Register offsets */

#define CCM_CSCR		IO_ADDR_CCM(0x0)

#define CCM_CSCR	(ccm + 0x00)

#define CCM_MPCTL0		IO_ADDR_CCM(0x4)

#define CCM_MPCTL0	(ccm + 0x04)

#define CCM_SPCTL0		IO_ADDR_CCM(0xc)

#define CCM_SPCTL0	(ccm + 0x0c)

#define CCM_PCDR0		IO_ADDR_CCM(0x18)

#define CCM_PCDR0	(ccm + 0x18)

#define CCM_PCDR1		IO_ADDR_CCM(0x1c)

#define CCM_PCDR1	(ccm + 0x1c)

#define CCM_PCCR0		IO_ADDR_CCM(0x20)

#define CCM_PCCR0	(ccm + 0x20)

#define CCM_PCCR1		IO_ADDR_CCM(0x24)

#define CCM_PCCR1	(ccm + 0x24)





static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };

static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };

static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };

static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };

static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };

static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };

static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };

static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };





enum imx21_clks {

static struct clk *clk[IMX21_CLK_MAX];

	dummy, ckil, ckih, fpm, ckih_div1p5, mpll_gate, spll_gate, fpm_gate,

static struct clk_onecell_data clk_data;

	ckih_gate, mpll_osc_sel, ipg, hclk, mpll_sel, spll_sel, ssi1_sel,

	ssi2_sel, usb_div, fclk, mpll, spll, nfc_div, ssi1_div, ssi2_div, per1,

	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,

	uart4_ipg_gate, cspi1_ipg_gate, cspi2_ipg_gate, ssi1_gate, ssi2_gate,

	sdhc1_ipg_gate, sdhc2_ipg_gate, gpio_gate, i2c_gate, dma_gate, usb_gate,

	emma_gate, ssi2_baud_gate, ssi1_baud_gate, lcdc_ipg_gate, nfc_gate,

	lcdc_hclk_gate, per4_gate, bmi_gate, usb_hclk_gate, slcdc_gate,

	slcdc_hclk_gate, emma_hclk_gate, brom_gate, dma_hclk_gate,

	csi_hclk_gate, cspi3_ipg_gate, wdog_gate, gpt1_ipg_gate, gpt2_ipg_gate,

	gpt3_ipg_gate, pwm_ipg_gate, rtc_gate, kpp_gate, owire_gate, clk_max

};



static struct clk *clk[clk_max];





int __init mx21_clocks_init(unsigned long lref, unsigned long href)

static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)

{

{

	clk[dummy] = imx_clk_fixed("dummy", 0);

	BUG_ON(!ccm);

	clk[ckil] = imx_clk_fixed("ckil", lref);



	clk[ckih] = imx_clk_fixed("ckih", href);

	clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);

	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);

	clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);

	clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);

	clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);



	clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);

	clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);

	clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);

	clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);



	clk[fpm_gate] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);

	clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);

	clk[ckih_gate] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);

	clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);

	clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));

	clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);

	clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);

	clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);

	clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);

	clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));

	clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));

	clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);

	clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));

	clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);

	clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));

	clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));

	clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));

	clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));

	clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);

	clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));

	clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);

	clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));



	clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);

	clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);

	clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);





	clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);

	clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);





	clk[nfc_div] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);

	clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);

	clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);



	clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);

	clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);



	clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);

	clk[per1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);

	clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);

	clk[per2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);



	clk[per3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);

	clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);

	clk[per4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);

	clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);



	clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);

	clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);

	clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);

	clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);



	clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);

	clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);

	clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);

	clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);

	clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);

	clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);

	clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);

	clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);

	clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);

	clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);

	clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);

	clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);

	clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);

	clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);

	clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);

	clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);

	clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);

	clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);

	clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);

	clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);

	clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);

	clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);

	clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);

	clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);

	clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);

	clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);

	clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);

	clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);

	clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);

	clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);

	clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);

	clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);

	clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);

	clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);

	clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);

	clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);

	clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);

	clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);

	clk[bmi_gate] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);

	clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);

	clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);

	clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);

	clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);

	clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);

	clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);

	clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);

	clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);

	clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);

	clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);

	clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);

	clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);

	clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);

	clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);

	clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);



	clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);

	clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);

	clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);

	clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);



	clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);

	clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);

	clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);

	clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);

	clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);

	clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);

	clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);

	clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);

	clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);

	clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);

	clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);

	clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);

	clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);

	clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);

	clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);

	clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);





	imx_check_clocks(clk, ARRAY_SIZE(clk));

	imx_check_clocks(clk, ARRAY_SIZE(clk));

}





	clk_register_clkdev(clk[per1], "per", "imx21-uart.0");

int __init mx21_clocks_init(unsigned long lref, unsigned long href)

	clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");

{

	clk_register_clkdev(clk[per1], "per", "imx21-uart.1");

	ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);

	clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");



	clk_register_clkdev(clk[per1], "per", "imx21-uart.2");

	_mx21_clocks_init(lref, href);

	clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");



	clk_register_clkdev(clk[per1], "per", "imx21-uart.3");

	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");

	clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");

	clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");

	clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");

	clk_register_clkdev(clk[per1], "per", "imx-gpt.0");

	clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");

	clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");

	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");

	clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");

	clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");

	clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");

	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");

	clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");

	clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");

	clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");

	clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");

	clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");

	clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");

	clk_register_clkdev(clk[per3], "per", "imx21-fb.0");

	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");

	clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");

	clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");

	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");

	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");

	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");

	clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");

	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");

	clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");

	clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");

	clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");

	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");

	clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");

	clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");

	clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");

	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");

	clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");

	clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");

	clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");

	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");

	clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");

	clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");

	clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");

	clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");

	clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");

	clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");

	clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");





	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);

	mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);





	return 0;

	return 0;

}

}



static void __init mx21_clocks_init_dt(struct device_node *np)

{

	ccm = of_iomap(np, 0);



	_mx21_clocks_init(32768, 26000000);



	clk_data.clks = clk;

	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));

}

CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);

include/dt-bindings/clock/imx21-clock.h

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/*

 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */



#ifndef __DT_BINDINGS_CLOCK_IMX21_H

#define __DT_BINDINGS_CLOCK_IMX21_H



#define IMX21_CLK_DUMMY			0

#define IMX21_CLK_CKIL			1

#define IMX21_CLK_CKIH			2

#define IMX21_CLK_FPM			3

#define IMX21_CLK_CKIH_DIV1P5		4

#define IMX21_CLK_MPLL_GATE		5

#define IMX21_CLK_SPLL_GATE		6

#define IMX21_CLK_FPM_GATE		7

#define IMX21_CLK_CKIH_GATE		8

#define IMX21_CLK_MPLL_OSC_SEL		9

#define IMX21_CLK_IPG			10

#define IMX21_CLK_HCLK			11

#define IMX21_CLK_MPLL_SEL		12

#define IMX21_CLK_SPLL_SEL		13

#define IMX21_CLK_SSI1_SEL		14

#define IMX21_CLK_SSI2_SEL		15

#define IMX21_CLK_USB_DIV		16

#define IMX21_CLK_FCLK			17

#define IMX21_CLK_MPLL			18

#define IMX21_CLK_SPLL			19

#define IMX21_CLK_NFC_DIV		20

#define IMX21_CLK_SSI1_DIV		21

#define IMX21_CLK_SSI2_DIV		22

#define IMX21_CLK_PER1			23

#define IMX21_CLK_PER2			24

#define IMX21_CLK_PER3			25

#define IMX21_CLK_PER4			26

#define IMX21_CLK_UART1_IPG_GATE	27

#define IMX21_CLK_UART2_IPG_GATE	28

#define IMX21_CLK_UART3_IPG_GATE	29

#define IMX21_CLK_UART4_IPG_GATE	30

#define IMX21_CLK_CSPI1_IPG_GATE	31

#define IMX21_CLK_CSPI2_IPG_GATE	32

#define IMX21_CLK_SSI1_GATE		33

#define IMX21_CLK_SSI2_GATE		34

#define IMX21_CLK_SDHC1_IPG_GATE	35

#define IMX21_CLK_SDHC2_IPG_GATE	36

#define IMX21_CLK_GPIO_GATE		37

#define IMX21_CLK_I2C_GATE		38

#define IMX21_CLK_DMA_GATE		39

#define IMX21_CLK_USB_GATE		40

#define IMX21_CLK_EMMA_GATE		41

#define IMX21_CLK_SSI2_BAUD_GATE	42

#define IMX21_CLK_SSI1_BAUD_GATE	43

#define IMX21_CLK_LCDC_IPG_GATE		44

#define IMX21_CLK_NFC_GATE		45

#define IMX21_CLK_LCDC_HCLK_GATE	46

#define IMX21_CLK_PER4_GATE		47

#define IMX21_CLK_BMI_GATE		48

#define IMX21_CLK_USB_HCLK_GATE		49

#define IMX21_CLK_SLCDC_GATE		50

#define IMX21_CLK_SLCDC_HCLK_GATE	51

#define IMX21_CLK_EMMA_HCLK_GATE	52

#define IMX21_CLK_BROM_GATE		53

#define IMX21_CLK_DMA_HCLK_GATE		54

#define IMX21_CLK_CSI_HCLK_GATE		55

#define IMX21_CLK_CSPI3_IPG_GATE	56

#define IMX21_CLK_WDOG_GATE		57

#define IMX21_CLK_GPT1_IPG_GATE		58

#define IMX21_CLK_GPT2_IPG_GATE		59

#define IMX21_CLK_GPT3_IPG_GATE		60

#define IMX21_CLK_PWM_IPG_GATE		61

#define IMX21_CLK_RTC_GATE		62

#define IMX21_CLK_KPP_GATE		63

#define IMX21_CLK_OWIRE_GATE		64

#define IMX21_CLK_MAX			65



#endif