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Commit 3532a6f0 authored by Naveen Yadav's avatar Naveen Yadav
Browse files

clk: qcom: gcc-bengal: Remove the throttle clocks 



Clocks that are sourcing to throttle block are required to be
controlled by RPM. Remove all control of them from the HLOS
clock driver.

Change-Id: Iec54ce7b034ac0fc1eda64459fce1efb589a9f21
Signed-off-by: default avatarNaveen Yadav <naveenky@codeaurora.org>
parent 07c19948

drivers/clk/qcom/gcc-bengal.c

+0 −46
Original line number Diff line number Diff line
@@ -2546,34 +2546,6 @@ static struct clk_branch gcc_cpuss_gnoc_clk = { 
	},

};



static struct clk_branch gcc_cpuss_throttle_core_clk = {

	.halt_reg = 0x2b180,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b180,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(30),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_cpuss_throttle_xo_clk = {

	.halt_reg = 0x2b17c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x2b17c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_throttle_xo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_disp_ahb_clk = {

	.halt_reg = 0x1700c,

	.halt_check = BRANCH_HALT,
@@ -2928,21 +2900,6 @@ static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 
	},

};



static struct clk_branch gcc_qmip_cpuss_cfg_ahb_clk = {

	.halt_reg = 0x2b178,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x2b178,

	.hwcg_bit = 1,

	.clkr = {

		.enable_reg = 0x79004,

		.enable_mask = BIT(18),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qmip_cpuss_cfg_ahb_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_qmip_disp_ahb_clk = {

	.halt_reg = 0x17018,

	.halt_check = BRANCH_HALT_VOTED,
@@ -3711,8 +3668,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { 
	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,

	[GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,

	[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,

	[GCC_CPUSS_THROTTLE_CORE_CLK] = &gcc_cpuss_throttle_core_clk.clkr,

	[GCC_CPUSS_THROTTLE_XO_CLK] = &gcc_cpuss_throttle_xo_clk.clkr,

	[GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,

	[GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,

	[GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
@@ -3740,7 +3695,6 @@ static struct clk_regmap *gcc_bengal_clocks[] = { 
	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,

	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,

	[GCC_QMIP_CPUSS_CFG_AHB_CLK] = &gcc_qmip_cpuss_cfg_ahb_clk.clkr,

	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,

	[GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,

	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,