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Commit 35087762 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2017-12-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 

- Allow internal page allocation to fail (Chris)
- More improvements on logs, dumps, and trace (Chris, Michal)
- Coffee Lake important fix for stolen memory (Lucas)
- Continue to make GPU reset more robust as well
   improving selftest coverage for it (Chris)
- Unifying debugfs return codes (Michal)
- Using existing helper for testing obj pages (Matthew)
- Organize and improve gem_request tracepoints (Lionel)
- Protect DDI port to DPLL map from theoretical race (Rodrigo)
- ... and consequently fixing the indentation on this DDI clk selection function (Chris)
- ... and consequently properly serializing non-blocking modesets (Ville)
- Add support for horizontal plane flipping on Cannonlake (Joonas)
- Two Cannonlake Workarounds for better stability (Rafael)
- Fix mess around PSR registers (DK)
- More Coffee Lake PCI IDs (Rodrigo)
- Remove CSS modifiers on pipe C of Geminilake (Krisman)
- Disable all planes for load detection (Ville)
- Reorg on i915 display headers (Michal)
- Avoid enabling movntdqa optimization on hypervisor guest (Changbin)

GVT:
- more mmio switch optimization (Weinan)
- cleanup i915_reg_t vs. offset usage (Zhenyu)
- move write protect handler out of mmio handler (Zhenyu)

* tag 'drm-intel-next-2017-12-22' of git://anongit.freedesktop.org/drm/drm-intel: (55 commits)
  drm/i915: Update DRIVER_DATE to 20171222
  drm/i915: Show HWSP in intel_engine_dump()
  drm/i915: Assert that the request is on the execution queue before being removed
  drm/i915/execlists: Show preemption progress in GEM_TRACE
  drm/i915: Put all non-blocking modesets onto an ordered wq
  drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+
  drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/a
  drm/i915: No need to power up PG2 for GMBUS on BXT
  drm/i915: Disable DC states around GMBUS on GLK
  drm/i915: Do not enable movntdqa optimization in hypervisor guest
  drm/i915: Dump device info at once
  drm/i915: Add pretty printer for runtime part of intel_device_info
  drm/i915: Update intel_device_info_runtime_init() parameter
  drm/i915: Move intel_device_info definitions to its own header
  drm/i915: Move opregion definitions to dedicated intel_opregion.h
  drm/i915: Move display related definitions to dedicated header
  drm/i915: Move some utility functions to i915_util.h
  drm/i915/gvt: move write protect handler out of mmio emulation function
  drm/i915/gvt: cleanup usage for typed mmio reg vs. offset
  drm/i915/gvt: Fix pipe A enable as default for vgpu
  ...
parents d50ce2ce cfe4982c

arch/x86/kernel/early-quirks.c

+1 −0
Original line number Diff line number Diff line
@@ -528,6 +528,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_SKL_IDS(&gen9_early_ops),

	INTEL_BXT_IDS(&gen9_early_ops),

	INTEL_KBL_IDS(&gen9_early_ops),

	INTEL_CFL_IDS(&gen9_early_ops),

	INTEL_GLK_IDS(&gen9_early_ops),

	INTEL_CNL_IDS(&gen9_early_ops),

};

drivers/gpu/drm/i915/Kconfig.debug

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ config DRM_I915_DEBUG 
	select SW_SYNC # signaling validation framework (igt/syncobj*)

	select DRM_I915_SW_FENCE_DEBUG_OBJECTS

	select DRM_I915_SELFTEST

	select DRM_I915_TRACE_GEM

        default n

        help

          Choose this option to turn on extra driver debugging that may affect
@@ -53,6 +52,7 @@ config DRM_I915_DEBUG_GEM 


config DRM_I915_TRACE_GEM

	bool "Insert extra ftrace output from the GEM internals"

	depends on DRM_I915_DEBUG_GEM

	select TRACING

	default n

	help

drivers/gpu/drm/i915/gvt/cmd_parser.c

+29 −10
Original line number Diff line number Diff line
@@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, 
	return 0;

}



static inline bool is_mocs_mmio(unsigned int offset)

{

	return ((offset >= 0xc800) && (offset <= 0xcff8)) ||

		((offset >= 0xb020) && (offset <= 0xb0a0));

}



static int mocs_cmd_reg_handler(struct parser_exec_state *s,

				unsigned int offset, unsigned int index)

{

	if (!is_mocs_mmio(offset))

		return -EINVAL;

	vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);

	return 0;

}



static int cmd_reg_handler(struct parser_exec_state *s,

	unsigned int offset, unsigned int index, char *cmd)

{
@@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
		return 0;

	}



	if (is_mocs_mmio(offset) &&

	    mocs_cmd_reg_handler(s, offset, index))

		return -EINVAL;



	if (is_force_nonpriv_mmio(offset) &&

		force_nonpriv_reg_handler(s, offset, index))

		return -EPERM;
@@ -1220,13 +1239,13 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
		return 0;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;

	} else {

		stride = (vgpu_vreg(s->vgpu, info->stride_reg) &

		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &

				GENMASK(15, 6)) >> 6;

		tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

	}



	if (stride != info->stride_val)
@@ -1245,21 +1264,21 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct intel_vgpu *vgpu = s->vgpu;



	set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),

	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

			      info->tile_val << 10);

	} else {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),

			      info->stride_val << 6);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

			      info->tile_val << 10);

	}



	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	intel_vgpu_trigger_virtual_event(vgpu, info->event);

	return 0;

}

drivers/gpu/drm/i915/gvt/display.c

+41 −40
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))

	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))

		return 0;



	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
@@ -74,7 +74,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 
	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))

		return -EINVAL;



	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)

	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)

		return 1;



	if (edp_pipe_is_enabled(vgpu) &&
@@ -169,103 +169,105 @@ static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 
static void emulate_monitor_status_change(struct intel_vgpu *vgpu)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

				SDE_PORTE_HOTPLUG_SPT);

		vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=

		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

				SKL_FUSE_DOWNLOAD_STATUS |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);

		vgpu_vreg(vgpu, LCPLL1_CTL) |=

		vgpu_vreg_t(vgpu, LCPLL1_CTL) |=

				LCPLL_PLL_ENABLE |

				LCPLL_PLL_LOCK;

		vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;

		vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;



	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_B << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_C << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_D << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

	}



	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

		if (IS_BROADWELL(dev_priv))

			vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_PORT_DP_A_HOTPLUG;

		else

			vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;



		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

	}



	/* Clear host CRT status, so guest couldn't detect this host CRT. */

	if (IS_BROADWELL(dev_priv))

		vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;

		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;



	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;

}



static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
@@ -282,7 +284,6 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,

				    int type, unsigned int resolution)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);



	if (WARN_ON(resolution >= GVT_EDID_NUM))
@@ -308,7 +309,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 
	port->type = type;



	emulate_monitor_status_change(vgpu);

	vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;



	return 0;

}
@@ -368,12 +369,12 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 
		if (!pipe_is_enabled(vgpu, pipe))

			continue;



		vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

		intel_vgpu_trigger_virtual_event(vgpu, event);

	}



	if (pipe_is_enabled(vgpu, pipe)) {

		vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;

		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;

		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);

	}

}

drivers/gpu/drm/i915/gvt/edid.c

+11 −11
Original line number Diff line number Diff line
@@ -95,9 +95,9 @@ static inline int get_port_from_gmbus0(u32 gmbus0) 


static void reset_gmbus_controller(struct intel_vgpu *vgpu)

{

	vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

	if (!vgpu->display.i2c_edid.edid_available)

		vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

}
@@ -123,16 +123,16 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, 
	vgpu->display.i2c_edid.state = I2C_GMBUS;

	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;



	vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

	vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;



	if (intel_vgpu_has_monitor_on_port(vgpu, port) &&

			!intel_vgpu_port_is_dp(vgpu, port)) {

		vgpu->display.i2c_edid.port = port;

		vgpu->display.i2c_edid.edid_available = true;

		vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

	} else

		vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

	return 0;

}
@@ -159,8 +159,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
		 * 2) HW_RDY bit asserted

		 */

		if (wvalue & GMBUS_SW_CLR_INT) {

			vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

			vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

		}



		/* For virtualization, we suppose that HW is always ready,
@@ -208,7 +208,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
				 * visible in gmbus interface)

				 */

				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;

				vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

				vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

			}

			break;

		case NIDX_NS_W:
@@ -220,7 +220,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
			 * START (-->INDEX) -->DATA

			 */

			i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;

			vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

			break;

		default:

			gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -256,7 +256,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 
	u32 reg_data = 0;



	/* Data can only be recevied if previous settings correct */

	if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

		if (byte_left <= 0) {

			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

			return 0;