ARM: dts: msm: Set (0) to core power control register for lagoon

1. Before vcodec regualtor hand off from SW to HW,
   driver makes sure GDSC is up and running. However
   SID registers are getting reset after regulator
   hand off from SW to HW and these are not
   retention registers on lagoon.
2. The reset of these registers is happening since
   core is in power off state during hand off and
   clock cc might possibly doing vcodec reset based
   on core power off status bit.
3. Hence setiing (0) to inititate power up process
   on core so that the SID register values are not
   lost.

Change-Id: Id45911ac2188a57b4c15bbcd8c492c76d366b43b