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Commit 346f5976 authored May 25, 2018 by Viresh Kumar Committed by Shawn Guo Jul 03, 2018

arm64: dts: freescale: Add missing cooling device properties for CPUs



The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

parent 7a2aeb91

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

+4 −1

Original line number	Diff line number	Diff line
		@@ -43,8 +43,8 @@
		reg = <0x0>;
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		#cooling-cells = <2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
		@@ -54,6 +54,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
		@@ -63,6 +64,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
		@@ -72,6 +74,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		l2: l2-cache {

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -50,6 +50,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
		@@ -59,6 +60,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
		@@ -68,6 +70,7 @@
		clocks = <&clockgen 1 0>;
		next-level-cache = <&l2>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		l2: l2-cache {

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -40,6 +40,7 @@
		reg = <0x1>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
		@@ -48,6 +49,7 @@
		reg = <0x2>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
		@@ -56,6 +58,7 @@
		reg = <0x3>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu4: cpu@100 {
		@@ -73,6 +76,7 @@
		reg = <0x101>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu6: cpu@102 {
		@@ -81,6 +85,7 @@
		reg = <0x102>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		cpu7: cpu@103 {
		@@ -89,6 +94,7 @@
		reg = <0x103>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PH20>;
		#cooling-cells = <2>;
		};

		CPU_PH20: cpu-ph20 {

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
		};

		cpu2: cpu@100 {
		@@ -48,6 +49,7 @@
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
		};

		cpu4: cpu@200 {
		@@ -67,6 +69,7 @@
		clocks = <&clockgen 1 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
		};

		cpu6: cpu@300 {
		@@ -86,6 +89,7 @@
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
		};

		cluster0_l2: l2-cache0 {

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

+4 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
		};

		cpu2: cpu@100 {
		@@ -48,6 +49,7 @@
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
		};

		cpu4: cpu@200 {
		@@ -67,6 +69,7 @@
		clocks = <&clockgen 1 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
		};

		cpu6: cpu@300 {
		@@ -86,6 +89,7 @@
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
		};

		cluster0_l2: l2-cache0 {