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Commit 340bce1b authored by Marc Zyngier's avatar Marc Zyngier Committed by Neeraj Upadhyay
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arm64: Add decoding macros for CP15_32 and CP15_64 traps 



So far, we don't have anything to help decoding ESR_ELx when dealing
with ESR_ELx_EC_CP15_{32,64}. As we're about to handle some of those,
let's add some useful macros.

Change-Id: I7b1e28df53b3f46983d5451962692093b7dd2d51
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Git-commit: bd7ac140b82f2bedfc792d8ccf9b2a108c1324f3
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


Signed-off-by: default avatarNeeraj Upadhyay <neeraju@codeaurora.org>
parent 71ba584c

arch/arm64/include/asm/esr.h

+52 −0
Original line number Diff line number Diff line
@@ -249,6 +249,58 @@ 


#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)



/*

 * ISS field definitions for CP15 accesses

 */

#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1

#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1

#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0



#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5

#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)

#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1

#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)

#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10

#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)

#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14

#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)

#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17

#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)



#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \

					 ESR_ELx_CP15_32_ISS_OP2_MASK | \

					 ESR_ELx_CP15_32_ISS_CRN_MASK | \

					 ESR_ELx_CP15_32_ISS_CRM_MASK | \

					 ESR_ELx_CP15_32_ISS_DIR_MASK)

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \

					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \

					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \

					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))



#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1

#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1

#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0



#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5

#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)



#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10

#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)



#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16

#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)

#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1

#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)



#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \

					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \

					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))



#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\

					 ESR_ELx_CP15_64_ISS_CRM_MASK | \

					 ESR_ELx_CP15_64_ISS_DIR_MASK)



#ifndef __ASSEMBLY__

#include <asm/types.h>