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Commit 33df85f6 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
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b43: N-PHY: update rev3+ gain control workarounds



This fixes workarounds on rev 6+ and cleans code slightly.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 25c15566
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+37 −24
Original line number Original line Diff line number Diff line
@@ -3197,7 +3197,7 @@ static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = {
			{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
			{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
			0x527E, /* invalid for external LNA! */
			0x527E, /* invalid for external LNA! */
			{ 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */
			{ 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */
			0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
			0x007E, 0x0066, 0x0000, /* low is invalid (the last one) */
			0x18, 0x18, 0x18,
			0x18, 0x18, 0x18,
			0x01D0, 0x5,
			0x01D0, 0x5,
		},
		},
@@ -3711,6 +3711,7 @@ const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
	struct b43_wldev *dev, bool ghz5, bool ext_lna)
	struct b43_wldev *dev, bool ghz5, bool ext_lna)
{
{
	struct b43_phy *phy = &dev->phy;
	struct nphy_gain_ctl_workaround_entry *e;
	struct nphy_gain_ctl_workaround_entry *e;
	u8 phy_idx;
	u8 phy_idx;


@@ -3729,27 +3730,38 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
	e = &nphy_gain_ctl_workaround[ghz5][phy_idx];
	e = &nphy_gain_ctl_workaround[ghz5][phy_idx];


	/* Some workarounds to the workarounds... */
	/* Some workarounds to the workarounds... */
	if (ghz5 && dev->phy.rev >= 6) {
	if (!ghz5) {
		if (dev->phy.radio_rev == 11 &&
		    !b43_is_40mhz(dev))
			e->cliplo_gain = 0x2d;
	} else if (!ghz5 && dev->phy.rev >= 5) {
		static const int gain_data[] = {0x0062, 0x0064, 0x006a, 0x106a,
						0x106c, 0x1074, 0x107c, 0x207c};
		u8 tr_iso = dev->dev->bus_sprom->fem.ghz2.tr_iso;
		u8 tr_iso = dev->dev->bus_sprom->fem.ghz2.tr_iso;


		if (ext_lna) {
		if (tr_iso > 7)
			tr_iso = 3;

		if (phy->rev >= 6) {
			static const int gain_data[] = { 0x106a, 0x106c, 0x1074,
							 0x107c, 0x007e, 0x107e,
							 0x207e, 0x307e, };

			e->cliplo_gain = gain_data[tr_iso];
		} else if (phy->rev == 5) {
			static const int gain_data[] = { 0x0062, 0x0064, 0x006a,
							 0x106a, 0x106c, 0x1074,
							 0x107c, 0x207c, };

			e->cliplo_gain = gain_data[tr_iso];
		}

		if (phy->rev >= 5 && ext_lna) {
			e->rfseq_init[0] &= ~0x4000;
			e->rfseq_init[0] &= ~0x4000;
			e->rfseq_init[1] &= ~0x4000;
			e->rfseq_init[1] &= ~0x4000;
			e->rfseq_init[2] &= ~0x4000;
			e->rfseq_init[2] &= ~0x4000;
			e->rfseq_init[3] &= ~0x4000;
			e->rfseq_init[3] &= ~0x4000;
			e->init_gain &= ~0x4000;
			e->init_gain &= ~0x4000;
		}
		}
		if (tr_iso > 7)
	} else {
			tr_iso = 3;
		if (phy->rev >= 6) {
		e->cliplo_gain = gain_data[tr_iso];
			if (phy->radio_rev == 11 && !b43_is_40mhz(dev))

				e->crsminu = 0x2d;
	} else if (ghz5 && dev->phy.rev == 4 && ext_lna) {
		} else if (phy->rev == 4 && ext_lna) {
			e->rfseq_init[0] &= ~0x4000;
			e->rfseq_init[0] &= ~0x4000;
			e->rfseq_init[1] &= ~0x4000;
			e->rfseq_init[1] &= ~0x4000;
			e->rfseq_init[2] &= ~0x4000;
			e->rfseq_init[2] &= ~0x4000;
@@ -3761,6 +3773,7 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
			e->rfseq_init[3] |= 0x1000;
			e->rfseq_init[3] |= 0x1000;
			e->init_gain |= 0x1000;
			e->init_gain |= 0x1000;
		}
		}
	}


	return e;
	return e;
}
}