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Commit 33d7885b authored by Chen Gong's avatar Chen Gong Committed by Tony Luck
Browse files

x86/mce: Update MCE severity condition check 



Update some SRAR severity conditions check to make it clearer,
according to latest Intel SDM Vol 3(June 2013), table 15-20.

Signed-off-by: default avatarChen Gong <gong.chen@linux.intel.com>
Acked-by: default avatarNaveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent 9e895ace

arch/x86/kernel/cpu/mcheck/mce-severity.c

+5 −10
Original line number Diff line number Diff line
@@ -110,22 +110,17 @@ static struct severity { 
	/* known AR MCACODs: */

#ifdef	CONFIG_MEMORY_FAILURE

	MCESEV(

		KEEP, "HT thread notices Action required: data load error",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),

		MCGMASK(MCG_STATUS_EIPV, 0)

		KEEP, "Action required but unaffected thread is continuable",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR),

		MCGMASK(MCG_STATUS_RIPV, MCG_STATUS_RIPV)

		),

	MCESEV(

		AR, "Action required: data load error",

		AR, "Action required: data load error in a user process",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),

		USER

		),

	MCESEV(

		KEEP, "HT thread notices Action required: instruction fetch error",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),

		MCGMASK(MCG_STATUS_EIPV, 0)

		),

	MCESEV(

		AR, "Action required: instruction fetch error",

		AR, "Action required: instruction fetch error in a user process",

		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),

		USER

		),