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Commit 33ce21d6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2018-06-08-2' of... 

Merge tag 'drm-intel-next-fixes-2018-06-08-2' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

First batch of i915 fixes for v4.18:
- gvt fixes that missed v4.17, potentially need to be backported
- eDP resolution regression revert
- remove broken nv12 special casing
- remove stale asserts from find active requests

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

Link: https://patchwork.freedesktop.org/patch/msgid/87y3fp4h15.fsf@intel.com
parents 68a14137 807cba65

drivers/gpu/drm/i915/gvt/cmd_parser.c

+1 −0
Original line number Diff line number Diff line
@@ -2909,6 +2909,7 @@ static int init_cmd_table(struct intel_gvt *gvt) 
		if (info) {

			gvt_err("%s %s duplicated\n", e->info->name,

					info->name);

			kfree(e);

			return -EEXIST;

		}

drivers/gpu/drm/i915/gvt/display.h

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
#define AUX_NATIVE_REPLY_NAK    (0x1 << 4)

#define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)



#define AUX_BURST_SIZE          16

#define AUX_BURST_SIZE          20



/* DPCD addresses */

#define DPCD_REV			0x000

drivers/gpu/drm/i915/gvt/handlers.c

+9 −4
Original line number Diff line number Diff line
@@ -903,11 +903,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 
		}



		/*

		 * Write request format: (command + address) occupies

		 * 3 bytes, followed by (len + 1) bytes of data.

		 * Write request format: Headr (command + address + size) occupies

		 * 4 bytes, followed by (len + 1) bytes of data. See details at

		 * intel_dp_aux_transfer().

		 */

		if (WARN_ON((len + 4) > AUX_BURST_SIZE))

		if ((len + 1 + 4) > AUX_BURST_SIZE) {

			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);

			return -EINVAL;

		}



		/* unpack data from vreg to buf */

		for (t = 0; t < 4; t++) {
@@ -971,8 +974,10 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 
		/*

		 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.

		 */

		if (WARN_ON((len + 2) > AUX_BURST_SIZE))

		if ((len + 2) > AUX_BURST_SIZE) {

			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);

			return -EINVAL;

		}



		/* read from virtual DPCD to vreg */

		/* first 4 bytes: [ACK][addr][addr+1][addr+2] */

drivers/gpu/drm/i915/gvt/kvmgt.c

+33 −1
Original line number Diff line number Diff line
@@ -123,6 +123,12 @@ static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 
		return -EINVAL;

	}



	if (!pfn_valid(pfn)) {

		gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn);

		vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &gfn, 1);

		return -EINVAL;

	}



	/* Setup DMA mapping. */

	page = pfn_to_page(pfn);

	*dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE,
@@ -583,6 +589,17 @@ static int intel_vgpu_open(struct mdev_device *mdev) 
	return ret;

}



static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu)

{

	struct eventfd_ctx *trigger;



	trigger = vgpu->vdev.msi_trigger;

	if (trigger) {

		eventfd_ctx_put(trigger);

		vgpu->vdev.msi_trigger = NULL;

	}

}



static void __intel_vgpu_release(struct intel_vgpu *vgpu)

{

	struct kvmgt_guest_info *info;
@@ -607,6 +624,8 @@ static void __intel_vgpu_release(struct intel_vgpu *vgpu) 
	info = (struct kvmgt_guest_info *)vgpu->handle;

	kvmgt_guest_exit(info);



	intel_vgpu_release_msi_eventfd_ctx(vgpu);



	vgpu->vdev.kvm = NULL;

	vgpu->handle = 0;

}
@@ -987,7 +1006,8 @@ static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, 
			return PTR_ERR(trigger);

		}

		vgpu->vdev.msi_trigger = trigger;

	}

	} else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count)

		intel_vgpu_release_msi_eventfd_ctx(vgpu);



	return 0;

}
@@ -1592,6 +1612,18 @@ static int kvmgt_inject_msi(unsigned long handle, u32 addr, u16 data) 
	info = (struct kvmgt_guest_info *)handle;

	vgpu = info->vgpu;



	/*

	 * When guest is poweroff, msi_trigger is set to NULL, but vgpu's

	 * config and mmio register isn't restored to default during guest

	 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe

	 * may be enabled, then once this vgpu is active, it will get inject

	 * vblank interrupt request. But msi_trigger is null until msi is

	 * enabled by guest. so if msi_trigger is null, success is still

	 * returned and don't inject interrupt into guest.

	 */

	if (vgpu->vdev.msi_trigger == NULL)

		return 0;



	if (eventfd_signal(vgpu->vdev.msi_trigger, 1) == 1)

		return 0;

drivers/gpu/drm/i915/i915_gem.c

+8 −9
Original line number Diff line number Diff line
@@ -2972,23 +2972,22 @@ i915_gem_find_active_request(struct intel_engine_cs *engine) 
	struct i915_request *request, *active = NULL;

	unsigned long flags;



	/* We are called by the error capture and reset at a random

	 * point in time. In particular, note that neither is crucially

	 * ordered with an interrupt. After a hang, the GPU is dead and we

	 * assume that no more writes can happen (we waited long enough for

	 * all writes that were in transaction to be flushed) - adding an

	/*

	 * We are called by the error capture, reset and to dump engine

	 * state at random points in time. In particular, note that neither is

	 * crucially ordered with an interrupt. After a hang, the GPU is dead

	 * and we assume that no more writes can happen (we waited long enough

	 * for all writes that were in transaction to be flushed) - adding an

	 * extra delay for a recent interrupt is pointless. Hence, we do

	 * not need an engine->irq_seqno_barrier() before the seqno reads.

	 * At all other times, we must assume the GPU is still running, but

	 * we only care about the snapshot of this moment.

	 */

	spin_lock_irqsave(&engine->timeline.lock, flags);

	list_for_each_entry(request, &engine->timeline.requests, link) {

		if (__i915_request_completed(request, request->global_seqno))

			continue;



		GEM_BUG_ON(request->engine != engine);

		GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,

				    &request->fence.flags));



		active = request;

		break;

	}