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Commit 33c5fd12 authored by David John's avatar David John Committed by Eric Anholt
Browse files

drm/i915: Disable SR when more than one pipe is enabled 



Self Refresh should be disabled on dual plane configs.  Otherwise, as
the SR watermark is not calculated for such configs, switching to non
VGA mode causes FIFO underrun and display flicker.

This fixes Korg Bug #14897.

Signed-off-by: default avatarDavid John <davidjon@xenontk.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Cc: stable@kernel.org
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 013d5aa2

drivers/gpu/drm/i915/intel_display.c

+12 −0
Original line number Diff line number Diff line
@@ -2520,6 +2520,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock, 
		sr_entries = roundup(sr_entries / cacheline_size, 1);

		DRM_DEBUG("self-refresh entries: %d\n", sr_entries);

		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

	} else {

		/* Turn off self refresh if both pipes are enabled */

		I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

					& ~FW_BLC_SELF_EN);

	}



	DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
@@ -2563,6 +2567,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, 
			srwm = 1;

		srwm &= 0x3f;

		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);

	} else {

		/* Turn off self refresh if both pipes are enabled */

		I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

					& ~FW_BLC_SELF_EN);

	}



	DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -2631,6 +2639,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, 
		if (srwm < 0)

			srwm = 1;

		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));

	} else {

		/* Turn off self refresh if both pipes are enabled */

		I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)

					& ~FW_BLC_SELF_EN);

	}



	DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",