Loading Documentation/admin-guide/hw-vuln/mds.rst +5 −2 Original line number Diff line number Diff line Loading @@ -265,8 +265,11 @@ time with the option "mds=". The valid arguments for this option are: ============ ============================================================= Not specifying this option is equivalent to "mds=full". Not specifying this option is equivalent to "mds=full". For processors that are affected by both TAA (TSX Asynchronous Abort) and MDS, specifying just "mds=off" without an accompanying "tsx_async_abort=off" will have no effect as the same mitigation is used for both vulnerabilities. Mitigation selection guide -------------------------- Loading Documentation/admin-guide/hw-vuln/tsx_async_abort.rst +4 −1 Original line number Diff line number Diff line Loading @@ -174,7 +174,10 @@ the option "tsx_async_abort=". The valid arguments for this option are: CPU is not vulnerable to cross-thread TAA attacks. ============ ============================================================= Not specifying this option is equivalent to "tsx_async_abort=full". Not specifying this option is equivalent to "tsx_async_abort=full". For processors that are affected by both TAA and MDS, specifying just "tsx_async_abort=off" without an accompanying "mds=off" will have no effect as the same mitigation is used for both vulnerabilities. The kernel command line also allows to control the TSX feature using the parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used Loading Documentation/admin-guide/kernel-parameters.txt +11 −0 Original line number Diff line number Diff line Loading @@ -2366,6 +2366,12 @@ SMT on vulnerable CPUs off - Unconditionally disable MDS mitigation On TAA-affected machines, mds=off can be prevented by an active TAA mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify tsx_async_abort=off too. Not specifying this option is equivalent to mds=full. Loading Loading @@ -4786,6 +4792,11 @@ vulnerable to cross-thread TAA attacks. off - Unconditionally disable TAA mitigation On MDS-affected machines, tsx_async_abort=off can be prevented by an active MDS mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify mds=off too. Not specifying this option is equivalent to tsx_async_abort=full. On CPUs which are MDS affected and deploy MDS mitigation, TAA mitigation is not Loading Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 SUBLEVEL = 85 SUBLEVEL = 87 EXTRAVERSION = NAME = "People's Front" Loading arch/arc/kernel/perf_event.c +2 −2 Original line number Diff line number Diff line Loading @@ -490,8 +490,8 @@ static int arc_pmu_device_probe(struct platform_device *pdev) /* loop thru all available h/w condition indexes */ for (j = 0; j < cc_bcr.c; j++) { write_aux_reg(ARC_REG_CC_INDEX, j); cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1); cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0)); cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1)); /* See if it has been mapped to a perf event_id */ for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) { Loading Loading
Documentation/admin-guide/hw-vuln/mds.rst +5 −2 Original line number Diff line number Diff line Loading @@ -265,8 +265,11 @@ time with the option "mds=". The valid arguments for this option are: ============ ============================================================= Not specifying this option is equivalent to "mds=full". Not specifying this option is equivalent to "mds=full". For processors that are affected by both TAA (TSX Asynchronous Abort) and MDS, specifying just "mds=off" without an accompanying "tsx_async_abort=off" will have no effect as the same mitigation is used for both vulnerabilities. Mitigation selection guide -------------------------- Loading
Documentation/admin-guide/hw-vuln/tsx_async_abort.rst +4 −1 Original line number Diff line number Diff line Loading @@ -174,7 +174,10 @@ the option "tsx_async_abort=". The valid arguments for this option are: CPU is not vulnerable to cross-thread TAA attacks. ============ ============================================================= Not specifying this option is equivalent to "tsx_async_abort=full". Not specifying this option is equivalent to "tsx_async_abort=full". For processors that are affected by both TAA and MDS, specifying just "tsx_async_abort=off" without an accompanying "mds=off" will have no effect as the same mitigation is used for both vulnerabilities. The kernel command line also allows to control the TSX feature using the parameter "tsx=" on CPUs which support TSX control. MSR_IA32_TSX_CTRL is used Loading
Documentation/admin-guide/kernel-parameters.txt +11 −0 Original line number Diff line number Diff line Loading @@ -2366,6 +2366,12 @@ SMT on vulnerable CPUs off - Unconditionally disable MDS mitigation On TAA-affected machines, mds=off can be prevented by an active TAA mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify tsx_async_abort=off too. Not specifying this option is equivalent to mds=full. Loading Loading @@ -4786,6 +4792,11 @@ vulnerable to cross-thread TAA attacks. off - Unconditionally disable TAA mitigation On MDS-affected machines, tsx_async_abort=off can be prevented by an active MDS mitigation as both vulnerabilities are mitigated with the same mechanism so in order to disable this mitigation, you need to specify mds=off too. Not specifying this option is equivalent to tsx_async_abort=full. On CPUs which are MDS affected and deploy MDS mitigation, TAA mitigation is not Loading
Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 SUBLEVEL = 85 SUBLEVEL = 87 EXTRAVERSION = NAME = "People's Front" Loading
arch/arc/kernel/perf_event.c +2 −2 Original line number Diff line number Diff line Loading @@ -490,8 +490,8 @@ static int arc_pmu_device_probe(struct platform_device *pdev) /* loop thru all available h/w condition indexes */ for (j = 0; j < cc_bcr.c; j++) { write_aux_reg(ARC_REG_CC_INDEX, j); cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); cc_name.indiv.word1 = read_aux_reg(ARC_REG_CC_NAME1); cc_name.indiv.word0 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME0)); cc_name.indiv.word1 = le32_to_cpu(read_aux_reg(ARC_REG_CC_NAME1)); /* See if it has been mapped to a perf event_id */ for (i = 0; i < ARRAY_SIZE(arc_pmu_ev_hw_map); i++) { Loading