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Commit 3358d2d9 authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Thierry Reding
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clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs 



On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent f55532a0

drivers/clk/tegra/clk-tegra210.c

+58 −0
Original line number Diff line number Diff line
@@ -175,6 +175,19 @@ 
#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)

#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)



#define SATA_PLL_CFG0				0x490

#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)

#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET	BIT(2)

#define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ		BIT(13)

#define SATA_PLL_CFG0_SEQ_ENABLE		BIT(24)



#define XUSBIO_PLL_CFG0				0x51c

#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)

#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL	BIT(2)

#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET	BIT(6)

#define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ	BIT(13)

#define XUSBIO_PLL_CFG0_SEQ_ENABLE		BIT(24)



#define UTMIPLL_HW_PWRDN_CFG0			0x52c

#define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK	BIT(31)

#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE	BIT(25)
@@ -416,6 +429,51 @@ static const char *mux_pllmcp_clkm[] = { 
#define PLLU_MISC0_WRITE_MASK		0xbfffffff

#define PLLU_MISC1_WRITE_MASK		0x00000007



void tegra210_xusb_pll_hw_control_enable(void)

{

	u32 val;



	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);

	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |

		 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);

	val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |

	       XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;

	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);

}

EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable);



void tegra210_xusb_pll_hw_sequence_start(void)

{

	u32 val;



	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);

	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);

}

EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start);



void tegra210_sata_pll_hw_control_enable(void)

{

	u32 val;



	val = readl_relaxed(clk_base + SATA_PLL_CFG0);

	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;

	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET |

	       SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ;

	writel_relaxed(val, clk_base + SATA_PLL_CFG0);

}

EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable);



void tegra210_sata_pll_hw_sequence_start(void)

{

	u32 val;



	val = readl_relaxed(clk_base + SATA_PLL_CFG0);

	val |= SATA_PLL_CFG0_SEQ_ENABLE;

	writel_relaxed(val, clk_base + SATA_PLL_CFG0);

}

EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);



static inline void _pll_misc_chk_default(void __iomem *base,

					struct tegra_clk_pll_params *params,

					u8 misc_num, u32 default_val, u32 mask)

include/linux/clk/tegra.h

+5 −0
Original line number Diff line number Diff line
@@ -121,4 +121,9 @@ static inline void tegra_cpu_clock_resume(void) 
}

#endif



extern void tegra210_xusb_pll_hw_control_enable(void);

extern void tegra210_xusb_pll_hw_sequence_start(void);

extern void tegra210_sata_pll_hw_control_enable(void);

extern void tegra210_sata_pll_hw_sequence_start(void);



#endif /* __LINUX_CLK_TEGRA_H_ */