Loading Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +11 −1 Original line number Diff line number Diff line Loading @@ -2,11 +2,21 @@ (CSPI/eCSPI) for i.MX Required properties: - compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi" - compatible : - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt - fsl,spi-num-chipselects : Contains the number of the chipselect - cs-gpios : Specifies the gpio pins to be used for chipselects. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" See the clock consumer binding, Documentation/devicetree/bindings/clock/clock-bindings.txt - dmas: DMA specifiers for tx and rx dma. See the DMA client binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. Loading Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +8 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,11 @@ Optional properties: nodes. If unspecified, a single SPI device without a chip select can be used. - dmas: Two DMA channel specifiers following the convention outlined in bindings/dma/dma.txt - dma-names: Names for the dma channels, if present. There must be at least one channel named "tx" for transmit and named "rx" for receive. SPI slave nodes must be children of the SPI master node and can contain properties described in Documentation/devicetree/bindings/spi/spi-bus.txt Loading @@ -51,6 +56,9 @@ Example: clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi8_default>; Loading Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +8 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,12 @@ Optional property: in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip select and the start of clock signal, at the start of a transfer. - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock signal and deactivating chip select, at the end of a transfer. Example: dspi0@4002c000 { Loading Loading @@ -43,6 +49,8 @@ dspi0@4002c000 { reg = <0>; linux,modalias = "m25p80"; modal = "at26df081a"; fsl,spi-cs-sck-delay = <100>; fsl,spi-sck-cs-delay = <50>; }; }; Loading Documentation/devicetree/bindings/spi/spi-img-spfi.txt +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ Required properties: - dma-names: Must include the following entries: - rx - tx - cs-gpios: Must specify the GPIOs used for chipselect lines. - #address-cells: Must be 1. - #size-cells: Must be 0. Loading Documentation/devicetree/bindings/spi/spi-rockchip.txt +4 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,9 @@ Optional Properties: - dmas: DMA specifiers for tx and rx dma. See the DMA client binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling Rx data (may need to be fine tuned for high capacitance lines). No delay (0) by default. Example: Loading @@ -33,6 +36,7 @@ Example: reg = <0xff110000 0x1000>; dmas = <&pdma1 11>, <&pdma1 12>; dma-names = "tx", "rx"; rx-sample-delay-ns = <10>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; Loading Loading
Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +11 −1 Original line number Diff line number Diff line Loading @@ -2,11 +2,21 @@ (CSPI/eCSPI) for i.MX Required properties: - compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi" - compatible : - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1 - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21 - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt - fsl,spi-num-chipselects : Contains the number of the chipselect - cs-gpios : Specifies the gpio pins to be used for chipselects. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" See the clock consumer binding, Documentation/devicetree/bindings/clock/clock-bindings.txt - dmas: DMA specifiers for tx and rx dma. See the DMA client binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. Loading
Documentation/devicetree/bindings/spi/qcom,spi-qup.txt +8 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,11 @@ Optional properties: nodes. If unspecified, a single SPI device without a chip select can be used. - dmas: Two DMA channel specifiers following the convention outlined in bindings/dma/dma.txt - dma-names: Names for the dma channels, if present. There must be at least one channel named "tx" for transmit and named "rx" for receive. SPI slave nodes must be children of the SPI master node and can contain properties described in Documentation/devicetree/bindings/spi/spi-bus.txt Loading @@ -51,6 +56,9 @@ Example: clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; dma-names = "rx", "tx"; pinctrl-names = "default"; pinctrl-0 = <&spi8_default>; Loading
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +8 −0 Original line number Diff line number Diff line Loading @@ -16,6 +16,12 @@ Optional property: in big endian mode, otherwise in native mode(same with CPU), for more detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip select and the start of clock signal, at the start of a transfer. - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock signal and deactivating chip select, at the end of a transfer. Example: dspi0@4002c000 { Loading Loading @@ -43,6 +49,8 @@ dspi0@4002c000 { reg = <0>; linux,modalias = "m25p80"; modal = "at26df081a"; fsl,spi-cs-sck-delay = <100>; fsl,spi-sck-cs-delay = <50>; }; }; Loading
Documentation/devicetree/bindings/spi/spi-img-spfi.txt +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ Required properties: - dma-names: Must include the following entries: - rx - tx - cs-gpios: Must specify the GPIOs used for chipselect lines. - #address-cells: Must be 1. - #size-cells: Must be 0. Loading
Documentation/devicetree/bindings/spi/spi-rockchip.txt +4 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,9 @@ Optional Properties: - dmas: DMA specifiers for tx and rx dma. See the DMA client binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. - rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling Rx data (may need to be fine tuned for high capacitance lines). No delay (0) by default. Example: Loading @@ -33,6 +36,7 @@ Example: reg = <0xff110000 0x1000>; dmas = <&pdma1 11>, <&pdma1 12>; dma-names = "tx", "rx"; rx-sample-delay-ns = <10>; #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; Loading