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Commit 32cae024 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Stephen Boyd
Browse files

clk: qcom: ipq8074: fix missing GPLL0 divider width 



GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent df964016

drivers/clk/qcom/gcc-ipq8074.c

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { 
static struct clk_alpha_pll_postdiv gpll0 = {

	.offset = 0x21000,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.width = 4,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "gpll0",

		.parent_names = (const char *[]){