Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 32b3fed4 authored by Rishabh Jain's avatar Rishabh Jain
Browse files

msm: camera: cdm: Flush all available FIFOs during reset 



Flush all the available FIFO during CDM reset to avoid
FIFO execution of stale entries.

CRs-Fixed: 2608094
Change-Id: I200d932f470849fe4c3935cbed96717531fe8b30
Signed-off-by: default avatarRishabh Jain <risjai@codeaurora.org>
parent cb02d402

drivers/cam_cdm/cam_cdm.h

+1 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 
/* BL_FIFO configurations*/

#define CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT 0x40

#define CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT 0x10

#define CAM_CDM_BL_FIFO_FLUSH_SHIFT 0x3



#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX 0x00

#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV2 0x01

drivers/cam_cdm/cam_cdm_hw_core.c

+8 −2
Original line number Diff line number Diff line
@@ -1248,6 +1248,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) 
	struct cam_cdm *cdm_core = NULL;

	long time_left;

	int i, rc = -EIO;

	int reset_val = 1;



	cdm_core = (struct cam_cdm *)cdm_hw->core_info;
@@ -1258,6 +1259,8 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) 
		mutex_lock(&cdm_core->bl_fifo[i].fifo_lock);



	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) {

		reset_val = reset_val |

			(1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT));

		if (cam_cdm_write_hw_reg(cdm_hw,

				cdm_core->offsets->irq_reg[i]->irq_mask,

				0x70003)) {
@@ -1267,7 +1270,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) 
	}



	if (cam_cdm_write_hw_reg(cdm_hw,

			cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) {

			cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) {

		CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset");

		goto end;

	}
@@ -1312,6 +1315,7 @@ int cam_hw_cdm_handle_error_info( 
	long time_left;

	int i, rc = -EIO, reset_hw_hdl = 0x0;

	uint32_t current_bl_data = 0, current_fifo = 0, current_tag = 0;

	int reset_val = 1;



	cdm_core = (struct cam_cdm *)cdm_hw->core_info;
@@ -1343,6 +1347,8 @@ int cam_hw_cdm_handle_error_info( 
	cam_hw_cdm_dump_core_debug_registers(cdm_hw);



	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) {

		reset_val = reset_val |

			(1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT));

		if (cam_cdm_write_hw_reg(cdm_hw,

				cdm_core->offsets->irq_reg[i]->irq_mask,

				0x70003)) {
@@ -1352,7 +1358,7 @@ int cam_hw_cdm_handle_error_info( 
	}



	if (cam_cdm_write_hw_reg(cdm_hw,

			cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) {

			cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) {

		CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset");

		goto end;

	}