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Commit 32a74164 authored by Chanwoo Choi's avatar Chanwoo Choi Committed by Eduardo Valentin
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thermal: exynos: Add support for TRIM_RELOAD feature at Exynos3250



This patch add support for TRIM_RELOAD feature at Exynos3250. The TMu of
Exynos3250 has two TRIMINFO_CON register and must need to set RELOAD bit
before reading TRIMINFO register.

Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Acked-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: default avatarAmit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: default avatarEduardo Valentin <edubezval@gmail.com>
parent 56c64da7
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+7 −2
Original line number Diff line number Diff line
@@ -87,6 +87,9 @@ struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS3250)
static const struct exynos_tmu_registers exynos3250_tmu_registers = {
	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
	.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON1,
	.triminfo_ctrl[1] = EXYNOS_TMU_TRIMINFO_CON2,
	.triminfo_ctrl_count = 2,
	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
	.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
@@ -147,8 +150,10 @@ static const struct exynos_tmu_registers exynos3250_tmu_registers = {
		.temp_level = 95, \
	}, \
	.freq_tab_count = 2, \
	.triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
	.triminfo_reload[1] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
	.registers = &exynos3250_tmu_registers, \
	.features = (TMU_SUPPORT_EMULATION | \
	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
			TMU_SUPPORT_EMUL_TIME)
#endif
@@ -169,7 +174,7 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
static const struct exynos_tmu_registers exynos4412_tmu_registers = {
	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
	.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON,
	.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON2,
	.triminfo_ctrl_count = 1,
	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
	.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
+5 −2
Original line number Diff line number Diff line
@@ -39,14 +39,17 @@
#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT	8
#define EXYNOS_TMU_CORE_EN_SHIFT	0

/* Exynos3250 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON1	0x10

/* Exynos4210 specific registers */
#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP	0x44
#define EXYNOS4210_TMU_REG_TRIG_LEVEL0	0x50

#define EXYNOS4210_TMU_TRIG_LEVEL_MASK	0x1111

/* Exynos5250 and Exynos4412 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON	0x14
/* Exynos5250, Exynos4412, Exynos3250 specific registers */
#define EXYNOS_TMU_TRIMINFO_CON2	0x14
#define EXYNOS_THD_TEMP_RISE		0x50
#define EXYNOS_THD_TEMP_FALL		0x54
#define EXYNOS_EMUL_CON		0x80