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Commit 326bd135 authored by David Dai's avatar David Dai Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: dispcc-kona: remove xo_clk_src, spdm and test clocks 



Let's remove the groups of unused SPDM, test clocks and also remove
the xo_clk_src that is keeping a persistent vote on MMCX due to the
fact that the disp_cc_xo_clk is marked as CRITICAL.

Change-Id: If36b032bea2650ddaf69e93c8512b39ec3d3f81b
Signed-off-by: default avatarDavid Dai <daidavid1@codeaurora.org>
parent f5f31790

drivers/clk/qcom/dispcc-kona.c

+0 −331
Original line number Diff line number Diff line
@@ -306,115 +306,6 @@ static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = { 
	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_dp_crypto_div_clk_src = {

	.reg = 0x6034,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_dp_crypto_div_clk_src",

		.parent_names =

			(const char *[]){ "disp_cc_mdss_dp_crypto_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_dp_pixel1_div_clk_src = {

	.reg = 0x603c,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_dp_pixel1_div_clk_src",

		.parent_names =

			(const char *[]){ "disp_cc_mdss_dp_pixel1_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_dp_pixel_div_clk_src = {

	.reg = 0x6038,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_dp_pixel_div_clk_src",

		.parent_names =

			(const char *[]){ "disp_cc_mdss_dp_pixel_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_mdp_div_clk_src = {

	.reg = 0x602c,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_mdp_div_clk_src",

		.parent_names = (const char *[]){ "disp_cc_mdss_mdp_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_pclk0_div_clk_src = {

	.reg = 0x6024,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_pclk0_div_clk_src",

		.parent_names =

			(const char *[]){ "disp_cc_mdss_pclk0_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_pclk1_div_clk_src = {

	.reg = 0x6028,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_pclk1_div_clk_src",

		.parent_names =

			(const char *[]){ "disp_cc_mdss_pclk1_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_mdss_spdm_rot_div_clk_src = {

	.reg = 0x6030,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_mdss_spdm_rot_div_clk_src",

		.parent_names = (const char *[]){ "disp_cc_mdss_rot_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};





static struct clk_regmap_div disp_cc_pll_test_div_clk_src = {

	.reg = 0x5014,

	.shift = 0,

	.width = 2,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "disp_cc_pll_test_div_clk_src",

		.parent_names = (const char *[]){ "disp_cc_pll0" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
@@ -978,38 +869,6 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { 
	},

};



static struct clk_rcg2 disp_cc_xo_clk_src = {

	.cmd_rcgr = 0x6044,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = disp_cc_parent_map_1,

	.freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_xo_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000},

	},

};



static struct clk_branch disp_cc_debug_clk = {

	.halt_reg = 0x500c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x500c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_ahb_clk = {

	.halt_reg = 0x2080,

	.halt_check = BRANCH_HALT,
@@ -1567,145 +1426,6 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 
	},

};



static struct clk_branch disp_cc_mdss_spdm_debug_clk = {

	.halt_reg = 0x6020,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6020,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_debug_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_dp_crypto_clk = {

	.halt_reg = 0x6014,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6014,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_dp_crypto_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_dp_crypto_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_dp_pixel1_clk = {

	.halt_reg = 0x601c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x601c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_dp_pixel1_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_dp_pixel1_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_dp_pixel_clk = {

	.halt_reg = 0x6018,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_dp_pixel_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_dp_pixel_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_mdp_clk = {

	.halt_reg = 0x600c,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x600c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_mdp_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_mdp_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_pclk0_clk = {

	.halt_reg = 0x6004,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_pclk0_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_pclk0_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_pclk1_clk = {

	.halt_reg = 0x6008,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_pclk1_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_pclk1_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_spdm_rot_clk = {

	.halt_reg = 0x6010,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x6010,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_spdm_rot_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_spdm_rot_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_mdss_vsync_clk = {

	.halt_reg = 0x2024,

	.halt_check = BRANCH_HALT,
@@ -1724,24 +1444,6 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { 
	},

};



static struct clk_branch disp_cc_pll_test_clk = {

	.halt_reg = 0x5018,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x5018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll_test_clk",

			.parent_names = (const char *[]){

				"disp_cc_pll_test_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch disp_cc_sleep_clk = {

	.halt_reg = 0x6078,

	.halt_check = BRANCH_HALT,
@@ -1768,10 +1470,6 @@ static struct clk_branch disp_cc_xo_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_xo_clk",

			.parent_names = (const char *[]){

				"disp_cc_xo_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},
@@ -1779,7 +1477,6 @@ static struct clk_branch disp_cc_xo_clk = { 
};



static struct clk_regmap *disp_cc_kona_clocks[] = {

	[DISP_CC_DEBUG_CLK] = &disp_cc_debug_clk.clkr,

	[DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,

	[DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,

	[DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
@@ -1842,46 +1539,18 @@ static struct clk_regmap *disp_cc_kona_clocks[] = { 
	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,

	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,

	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,

	[DISP_CC_MDSS_SPDM_DEBUG_CLK] = &disp_cc_mdss_spdm_debug_clk.clkr,

	[DISP_CC_MDSS_SPDM_DP_CRYPTO_CLK] =

		&disp_cc_mdss_spdm_dp_crypto_clk.clkr,

	[DISP_CC_MDSS_SPDM_DP_CRYPTO_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_dp_crypto_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_DP_PIXEL1_CLK] =

		&disp_cc_mdss_spdm_dp_pixel1_clk.clkr,

	[DISP_CC_MDSS_SPDM_DP_PIXEL1_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_dp_pixel1_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_DP_PIXEL_CLK] = &disp_cc_mdss_spdm_dp_pixel_clk.clkr,

	[DISP_CC_MDSS_SPDM_DP_PIXEL_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_dp_pixel_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_MDP_CLK] = &disp_cc_mdss_spdm_mdp_clk.clkr,

	[DISP_CC_MDSS_SPDM_MDP_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_mdp_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_PCLK0_CLK] = &disp_cc_mdss_spdm_pclk0_clk.clkr,

	[DISP_CC_MDSS_SPDM_PCLK0_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_pclk0_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_PCLK1_CLK] = &disp_cc_mdss_spdm_pclk1_clk.clkr,

	[DISP_CC_MDSS_SPDM_PCLK1_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_pclk1_div_clk_src.clkr,

	[DISP_CC_MDSS_SPDM_ROT_CLK] = &disp_cc_mdss_spdm_rot_clk.clkr,

	[DISP_CC_MDSS_SPDM_ROT_DIV_CLK_SRC] =

		&disp_cc_mdss_spdm_rot_div_clk_src.clkr,

	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,

	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

	[DISP_CC_PLL0] = &disp_cc_pll0.clkr,

	[DISP_CC_PLL1] = &disp_cc_pll1.clkr,

	[DISP_CC_PLL_TEST_CLK] = &disp_cc_pll_test_clk.clkr,

	[DISP_CC_PLL_TEST_DIV_CLK_SRC] = &disp_cc_pll_test_div_clk_src.clkr,

	[DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,

	[DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,

	[DISP_CC_XO_CLK] = &disp_cc_xo_clk.clkr,

	[DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr,

};



static const struct qcom_reset_map disp_cc_kona_resets[] = {

	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },

	[DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },

	[DISP_CC_MDSS_SPDM_BCR] = { 0x6000 },

};



static const struct regmap_config disp_cc_kona_regmap_config = {

include/dt-bindings/clock/qcom,dispcc-kona.h

+70 −88
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KONA_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KONA_H



#define DISP_CC_DEBUG_CLK					0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				5

#define DISP_CC_MDSS_BYTE0_INTF_CLK				6

#define DISP_CC_MDSS_BYTE1_CLK					7

#define DISP_CC_MDSS_BYTE1_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				9

#define DISP_CC_MDSS_BYTE1_INTF_CLK				10

#define DISP_CC_MDSS_DP_AUX1_CLK				11

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				12

#define DISP_CC_MDSS_DP_AUX_CLK					13

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				15

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK				17

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				18

#define DISP_CC_MDSS_DP_LINK1_CLK				19

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				20

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			21

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK				23

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				24

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			25

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK				27

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK				29

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				30

#define DISP_CC_MDSS_DP_PIXEL_CLK				31

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				32

#define DISP_CC_MDSS_EDP_AUX_CLK				33

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				34

#define DISP_CC_MDSS_EDP_GTC_CLK				35

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				36

#define DISP_CC_MDSS_EDP_LINK_CLK				37

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				38

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			39

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				40

#define DISP_CC_MDSS_EDP_PIXEL_CLK				41

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				42

#define DISP_CC_MDSS_ESC0_CLK					43

#define DISP_CC_MDSS_ESC0_CLK_SRC				44

#define DISP_CC_MDSS_ESC1_CLK					45

#define DISP_CC_MDSS_ESC1_CLK_SRC				46

#define DISP_CC_MDSS_MDP_CLK					47

#define DISP_CC_MDSS_MDP_CLK_SRC				48

#define DISP_CC_MDSS_MDP_LUT_CLK				49

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				50

#define DISP_CC_MDSS_PCLK0_CLK					51

#define DISP_CC_MDSS_PCLK0_CLK_SRC				52

#define DISP_CC_MDSS_PCLK1_CLK					53

#define DISP_CC_MDSS_PCLK1_CLK_SRC				54

#define DISP_CC_MDSS_ROT_CLK					55

#define DISP_CC_MDSS_ROT_CLK_SRC				56

#define DISP_CC_MDSS_RSCC_AHB_CLK				57

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				58

#define DISP_CC_MDSS_SPDM_DEBUG_CLK				59

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_CLK				60

#define DISP_CC_MDSS_SPDM_DP_CRYPTO_DIV_CLK_SRC			61

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_CLK				62

#define DISP_CC_MDSS_SPDM_DP_PIXEL1_DIV_CLK_SRC			63

#define DISP_CC_MDSS_SPDM_DP_PIXEL_CLK				64

#define DISP_CC_MDSS_SPDM_DP_PIXEL_DIV_CLK_SRC			65

#define DISP_CC_MDSS_SPDM_MDP_CLK				66

#define DISP_CC_MDSS_SPDM_MDP_DIV_CLK_SRC			67

#define DISP_CC_MDSS_SPDM_PCLK0_CLK				68

#define DISP_CC_MDSS_SPDM_PCLK0_DIV_CLK_SRC			69

#define DISP_CC_MDSS_SPDM_PCLK1_CLK				70

#define DISP_CC_MDSS_SPDM_PCLK1_DIV_CLK_SRC			71

#define DISP_CC_MDSS_SPDM_ROT_CLK				72

#define DISP_CC_MDSS_SPDM_ROT_DIV_CLK_SRC			73

#define DISP_CC_MDSS_VSYNC_CLK					74

#define DISP_CC_MDSS_VSYNC_CLK_SRC				75

#define DISP_CC_PLL0						76

#define DISP_CC_PLL1						77

#define DISP_CC_PLL_TEST_CLK					78

#define DISP_CC_PLL_TEST_DIV_CLK_SRC				79

#define DISP_CC_SLEEP_CLK					80

#define DISP_CC_SLEEP_CLK_SRC					81

#define DISP_CC_XO_CLK						82

#define DISP_CC_XO_CLK_SRC					83



#define MDSS_CORE_GDSC						0

/* DISP_CC clocks */

#define DISP_CC_MDSS_AHB_CLK					0

#define DISP_CC_MDSS_AHB_CLK_SRC				1

#define DISP_CC_MDSS_BYTE0_CLK					2

#define DISP_CC_MDSS_BYTE0_CLK_SRC				3

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_BYTE1_CLK					6

#define DISP_CC_MDSS_BYTE1_CLK_SRC				7

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				8

#define DISP_CC_MDSS_BYTE1_INTF_CLK				9

#define DISP_CC_MDSS_DP_AUX1_CLK				10

#define DISP_CC_MDSS_DP_AUX1_CLK_SRC				11

#define DISP_CC_MDSS_DP_AUX_CLK					12

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				13

#define DISP_CC_MDSS_DP_CRYPTO1_CLK				14

#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC				15

#define DISP_CC_MDSS_DP_CRYPTO_CLK				16

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				17

#define DISP_CC_MDSS_DP_LINK1_CLK				18

#define DISP_CC_MDSS_DP_LINK1_CLK_SRC				19

#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC			20

#define DISP_CC_MDSS_DP_LINK1_INTF_CLK				21

#define DISP_CC_MDSS_DP_LINK_CLK				22

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				23

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			24

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				25

#define DISP_CC_MDSS_DP_PIXEL1_CLK				26

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				27

#define DISP_CC_MDSS_DP_PIXEL2_CLK				28

#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC				29

#define DISP_CC_MDSS_DP_PIXEL_CLK				30

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				31

#define DISP_CC_MDSS_EDP_AUX_CLK				32

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC				33

#define DISP_CC_MDSS_EDP_GTC_CLK				34

#define DISP_CC_MDSS_EDP_GTC_CLK_SRC				35

#define DISP_CC_MDSS_EDP_LINK_CLK				36

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC				37

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC			38

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK				39

#define DISP_CC_MDSS_EDP_PIXEL_CLK				40

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC				41

#define DISP_CC_MDSS_ESC0_CLK					42

#define DISP_CC_MDSS_ESC0_CLK_SRC				43

#define DISP_CC_MDSS_ESC1_CLK					44

#define DISP_CC_MDSS_ESC1_CLK_SRC				45

#define DISP_CC_MDSS_MDP_CLK					46

#define DISP_CC_MDSS_MDP_CLK_SRC				47

#define DISP_CC_MDSS_MDP_LUT_CLK				48

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				49

#define DISP_CC_MDSS_PCLK0_CLK					50

#define DISP_CC_MDSS_PCLK0_CLK_SRC				51

#define DISP_CC_MDSS_PCLK1_CLK					52

#define DISP_CC_MDSS_PCLK1_CLK_SRC				53

#define DISP_CC_MDSS_ROT_CLK					54

#define DISP_CC_MDSS_ROT_CLK_SRC				55

#define DISP_CC_MDSS_RSCC_AHB_CLK				56

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				57

#define DISP_CC_MDSS_VSYNC_CLK					58

#define DISP_CC_MDSS_VSYNC_CLK_SRC				59

#define DISP_CC_PLL0						60

#define DISP_CC_PLL1						61

#define DISP_CC_SLEEP_CLK					62

#define DISP_CC_SLEEP_CLK_SRC					63

#define DISP_CC_XO_CLK						64



/* DISP_CC resets */

#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_RSCC_BCR					1

#define DISP_CC_MDSS_SPDM_BCR					2



#endif