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Commit 326b06a8 authored by Mark Brown's avatar Mark Brown
Browse files

Merge remote-tracking branch 'asoc/topic/core' into asoc-next

parents 92b2e81d 9bffb1fb

Makefile

+5 −3
Original line number Diff line number Diff line 
VERSION = 3

PATCHLEVEL = 7

SUBLEVEL = 0

EXTRAVERSION = -rc7

EXTRAVERSION =

NAME = Terrified Chipmunk



# *DOCUMENTATION*
@@ -1321,10 +1321,12 @@ kernelversion: 


# Clear a bunch of variables before executing the submake

tools/: FORCE

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/

	$(Q)mkdir -p $(objtree)/tools

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= O=$(objtree) subdir=tools -C $(src)/tools/



tools/%: FORCE

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= -C $(src)/tools/ $*

	$(Q)mkdir -p $(objtree)/tools

	$(Q)$(MAKE) LDFLAGS= MAKEFLAGS= O=$(objtree) subdir=tools -C $(src)/tools/ $*



# Single targets

# ---------------------------------------------------------------------------

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -547,6 +547,7 @@ config ARCH_KIRKWOOD 
	select CPU_FEROCEON

	select GENERIC_CLOCKEVENTS

	select PCI

	select PCI_QUIRKS

	select PLAT_ORION_LEGACY

	help

	  Support for the following Marvell Kirkwood series SoCs:

arch/arm/boot/compressed/head.S

+13 −1
Original line number Diff line number Diff line
@@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size 
		mov	pc, lr

ENDPROC(__setup_mmu)



@ Enable unaligned access on v6, to allow better code generation

@ for the decompressor C code:

__armv6_mmu_cache_on:

		mrc	p15, 0, r0, c1, c0, 0	@ read SCTLR

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

		mcr	p15, 0, r0, c1, c0, 0	@ write SCTLR

		b	__armv4_mmu_cache_on



__arm926ejs_mmu_cache_on:

#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

		mov	r0, #4			@ put dcache in WT mode
@@ -694,6 +703,9 @@ __armv7_mmu_cache_on: 
		bic	r0, r0, #1 << 28	@ clear SCTLR.TRE

		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement

		orr	r0, r0, #0x003c		@ write buffer

		bic	r0, r0, #2		@ A (no unaligned access fault)

		orr	r0, r0, #1 << 22	@ U (v6 unaligned access model)

						@ (needed for ARM1176)

#ifdef CONFIG_MMU

#ifdef CONFIG_CPU_ENDIAN_BE8

		orr	r0, r0, #1 << 25	@ big-endian page tables
@@ -914,7 +926,7 @@ proc_types: 


		.word	0x0007b000		@ ARMv6

		.word	0x000ff000

		W(b)	__armv4_mmu_cache_on

		W(b)	__armv6_mmu_cache_on

		W(b)	__armv4_mmu_cache_off

		W(b)	__armv6_mmu_cache_flush

arch/arm/common/timer-sp.c

+1 −1
Original line number Diff line number Diff line
@@ -162,7 +162,6 @@ static struct clock_event_device sp804_clockevent = { 
	.set_mode	= sp804_set_mode,

	.set_next_event	= sp804_set_next_event,

	.rating		= 300,

	.cpumask	= cpu_all_mask,

};



static struct irqaction sp804_timer_irq = {
@@ -185,6 +184,7 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, 
	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);

	evt->name = name;

	evt->irq = irq;

	evt->cpumask = cpu_possible_mask;



	setup_irq(irq, &sp804_timer_irq);

	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);

arch/arm/mach-dove/include/mach/pm.h

+1 −1
Original line number Diff line number Diff line
@@ -63,7 +63,7 @@ static inline int pmu_to_irq(int pin) 


static inline int irq_to_pmu(int irq)

{

	if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)

	if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)

		return irq - IRQ_DOVE_PMU_START;



	return -EINVAL;