Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3230d011 authored by Igor Russkikh's avatar Igor Russkikh Committed by David S. Miller
Browse files

net: aquantia: Fix register definitions to linux style



Original driver code had internal registers and masks declarations
in low case and without any prefix.
Here we make all these uppercase and add already used HW_ATL prefix
to recognize these.

Signed-off-by: default avatarIgor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent db550615
Loading
Loading
Loading
Loading
+4 −3
Original line number Original line Diff line number Diff line
@@ -381,14 +381,15 @@ static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
	hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
	hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);


	/* Force limit MRRS on RDM/TDM to 2K */
	/* Force limit MRRS on RDM/TDM to 2K */
	val = aq_hw_read_reg(self, pci_reg_control6_adr);
	val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
	aq_hw_write_reg(self, pci_reg_control6_adr, (val & ~0x707) | 0x404);
	aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
			(val & ~0x707) | 0x404);


	/* TX DMA total request limit. B0 hardware is not capable to
	/* TX DMA total request limit. B0 hardware is not capable to
	 * handle more than (8K-MRRS) incoming DMA data.
	 * handle more than (8K-MRRS) incoming DMA data.
	 * Value 24 in 256byte units
	 * Value 24 in 256byte units
	 */
	 */
	aq_hw_write_reg(self, tx_dma_total_req_limit_adr, 24);
	aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);


	/* Reset link status and read out initial hardware counters */
	/* Reset link status and read out initial hardware counters */
	self->aq_link_status.mbps = 0;
	self->aq_link_status.mbps = 0;