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Commit 32087d14 authored by Praveen Paneri's avatar Praveen Paneri Committed by Rodrigo Vivi
Browse files

drm/i915: enable WaDisableDopClkGating for skl 



This WA is required when decoupled frequencies for slice and unslice
are enabled. This disables DOP clock gating for skl.

v2: enable the WA for all gen9 platforms (not just for SKL GT4 where
    the hang issue is originally reported) to avoid rare hangs (David)
v3: as per WaDatabase, enable it only for SKL (Rodrigo)

Cc: David Weinehall <david.weinehall@linux.intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: default avatarPraveen Paneri <praveen.paneri@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1501781530-8186-1-git-send-email-praveen.paneri@intel.com
parent 23247d71

drivers/gpu/drm/i915/intel_pm.c

+6 −0
Original line number Diff line number Diff line
@@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) 
	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */

	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |

		   ILK_DPFC_DISABLE_DUMMY0);



	if (IS_SKYLAKE(dev_priv)) {

		/* WaDisableDopClockGating */

		I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)

			   & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	}

}



static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)