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Commit 3176810d authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros 



Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ba7d5a22

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c

+16 −16
Original line number Diff line number Diff line
@@ -172,7 +172,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 
	/* Check sOS sign of life register to confirm sys driver and sOS

	 * are already been loaded.

	 */

	sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));

	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

	if (sol_reg)

		return 0;
@@ -188,10 +188,10 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 
	memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);



	/* Provide the sys driver to bootrom */

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

	       (uint32_t)(psp->fw_pri_mc_addr >> 20));

	psp_gfxdrv_command_reg = 1 << 16;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

	       psp_gfxdrv_command_reg);



	/* there might be handshake issue with hardware which needs delay */
@@ -213,7 +213,7 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 
	/* Check sOS sign of life register to confirm sys driver and sOS

	 * are already been loaded.

	 */

	sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81));

	sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);

	if (sol_reg)

		return 0;
@@ -229,17 +229,17 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 
	memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);



	/* Provide the PSP secure OS to bootrom */

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36),

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,

	       (uint32_t)(psp->fw_pri_mc_addr >> 20));

	psp_gfxdrv_command_reg = 2 << 16;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,

	       psp_gfxdrv_command_reg);



	/* there might be handshake issue with hardware which needs delay */

	mdelay(20);

#if 0

	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),

			   RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)),

			   RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),

			   0, true);

#endif
@@ -299,17 +299,17 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type) 


	/* Write low address of the ring to C2PMSG_69 */

	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);

	/* Write high address of the ring to C2PMSG_70 */

	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);

	/* Write size of ring to C2PMSG_71 */

	psp_ring_reg = ring->ring_size;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);

	/* Write the ring initialization command to C2PMSG_64 */

	psp_ring_reg = ring_type;

	psp_ring_reg = psp_ring_reg << 16;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);



	/* there might be handshake issue with hardware which needs delay */

	mdelay(20);
@@ -332,7 +332,7 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type) 


	/* Write the ring destroy command to C2PMSG_64 */

	psp_ring_reg = 3 << 16;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);



	/* there might be handshake issue with hardware which needs delay */

	mdelay(20);
@@ -361,7 +361,7 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, 
	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;



	/* KM (GPCOM) prepare write pointer */

	psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67));

	psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);



	/* Update KM RB frame pointer to new frame */

	/* write_frame ptr increments by size of rb_frame in bytes */
@@ -383,7 +383,7 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, 


	/* Update the write Pointer in DWORDs */

	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;

	WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg);

	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);



	return 0;

}
@@ -515,7 +515,7 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 
	uint32_t reg;



	reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000;

	WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg);

	reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2));

	WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg);

	reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2);

	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;

}