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Commit 31513207 authored by Matt Brown's avatar Matt Brown Committed by Michael Ellerman
Browse files

powerpc: Remove unused flush_dcache_phys_range() 



The flush_dcache_phys_range() function is no longer used in the
kernel. The last usage was removed in c40785ad ("powerpc/dart: Use
a cachable DART").

This patch removes the function and declaration.

Signed-off-by: default avatarMatt Brown <matthew.brown.dev@gmail.com>
[mpe: Munge change log, include commit that removed last user]
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent aa9532d4

arch/powerpc/include/asm/cacheflush.h

+0 −1
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ static inline void invalidate_dcache_range(unsigned long start, 
#ifdef CONFIG_PPC64

extern void flush_dcache_range(unsigned long start, unsigned long stop);

extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);

extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);

#endif



#define copy_to_user_page(vma, page, vaddr, dst, src, len) \

arch/powerpc/kernel/misc_64.S

+0 −38
Original line number Diff line number Diff line
@@ -144,44 +144,6 @@ _GLOBAL_TOC(flush_dcache_range) 
	blr

EXPORT_SYMBOL(flush_dcache_range)



/*

 * Like above, but works on non-mapped physical addresses.

 * Use only for non-LPAR setups ! It also assumes real mode

 * is cacheable. Used for flushing out the DART before using

 * it as uncacheable memory 

 *

 * flush_dcache_phys_range(unsigned long start, unsigned long stop)

 *

 *    flush all bytes from start to stop-1 inclusive

 */

_GLOBAL(flush_dcache_phys_range)

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */

	addi	r5,r7,-1

	andc	r6,r3,r5		/* round low to line bdy */

	subf	r8,r6,r4		/* compute length */

	add	r8,r8,r5		/* ensure we get enough */

	lwz	r9,DCACHEL1LOGBLOCKSIZE(r10)	/* Get log-2 of dcache block size */

	srw.	r8,r8,r9		/* compute line count */

	beqlr				/* nothing to do? */

	mfmsr	r5			/* Disable MMU Data Relocation */

	ori	r0,r5,MSR_DR

	xori	r0,r0,MSR_DR

	sync

	mtmsr	r0

	sync

	isync

	mtctr	r8

0:	dcbst	0,r6

	add	r6,r6,r7

	bdnz	0b

	sync

	isync

	mtmsr	r5			/* Re-enable MMU Data Relocation */

	sync

	isync

	blr



_GLOBAL(flush_inval_dcache_range)

 	ld	r10,PPC64_CACHES@toc(r2)

	lwz	r7,DCACHEL1BLOCKSIZE(r10)	/* Get dcache block size */