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Commit 30ee5814 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
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ARM: dts: rockchip: set default rates for core clocks on rk322x 



Set sane default frequencies for CPLL, GPLL and some other core clocks
on the rk322x.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarFrank Wang <frank.wang@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 738e4511

arch/arm/boot/dts/rk322x.dtsi

+12 −2
Original line number Diff line number Diff line
@@ -346,8 +346,18 @@ 
		rockchip,grf = <&grf>;

		#clock-cells = <1>;

		#reset-cells = <1>;

		assigned-clocks = <&cru PLL_GPLL>;

		assigned-clock-rates = <594000000>;

		assigned-clocks =

			<&cru PLL_GPLL>, <&cru ARMCLK>,

			<&cru PLL_CPLL>, <&cru ACLK_PERI>,

			<&cru HCLK_PERI>, <&cru PCLK_PERI>,

			<&cru ACLK_CPU>, <&cru HCLK_CPU>,

			<&cru PCLK_CPU>;

		assigned-clock-rates =

			<594000000>, <816000000>,

			<500000000>, <150000000>,

			<150000000>, <75000000>,

			<150000000>, <150000000>,

			<75000000>;

	};



	thermal-zones {