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Commit 30d430d9 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'uniphier-dt-v4.9' of... 

Merge tag 'uniphier-dt-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt

Merge "UniPhier ARM SoC DT updates for v4.9" from Masahiro Yamada:

* Match DT names other projects and documents
* Switch over to PSCI
* Use clock/reset drivers
* Misc

* tag 'uniphier-dt-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
  ARM: dts: uniphier: add specific compatible to SoC-Glue node
  ARM: dts: uniphier: use clock/reset controllers
  ARM: dts: uniphier: switch over to PSCI
  ARM: dts: uniphier: match DT names to other projects and documents
  ARM: dts: uniphier: remove a whitespace after tabs
parents 6f7f9e44 cb165937

arch/arm/boot/dts/Makefile

+9 −9
Original line number Diff line number Diff line
@@ -836,15 +836,15 @@ dtb-$(CONFIG_ARCH_U8500) += \ 
	ste-ccu8540.dtb \

	ste-ccu9540.dtb

dtb-$(CONFIG_ARCH_UNIPHIER) += \

	uniphier-ph1-ld4-ref.dtb \

	uniphier-ph1-ld6b-ref.dtb \

	uniphier-ph1-pro4-ace.dtb \

	uniphier-ph1-pro4-ref.dtb \

	uniphier-ph1-pro4-sanji.dtb \

	uniphier-ph1-sld3-ref.dtb \

	uniphier-ph1-sld8-ref.dtb \

	uniphier-proxstream2-gentil.dtb \

	uniphier-proxstream2-vodka.dtb

	uniphier-ld4-ref.dtb \

	uniphier-ld6b-ref.dtb \

	uniphier-pro4-ace.dtb \

	uniphier-pro4-ref.dtb \

	uniphier-pro4-sanji.dtb \

	uniphier-pxs2-gentil.dtb \

	uniphier-pxs2-vodka.dtb \

	uniphier-sld3-ref.dtb \

	uniphier-sld8-ref.dtb

dtb-$(CONFIG_ARCH_VERSATILE) += \

	versatile-ab.dtb \

	versatile-pb.dtb

arch/arm/boot/dts/uniphier-common32.dtsi

+56 −7
Original line number Diff line number Diff line 
/*

 * Device Tree Source commonly used by UniPhier ARM SoCs

 *

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual
@@ -45,6 +46,11 @@ 
/include/ "skeleton.dtsi"



/ {

	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	clocks {

		refclk: ref {

			#clock-cells = <0>;
@@ -66,7 +72,7 @@ 
			interrupts = <0 33 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart0>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 0>;

		};



		serial1: serial@54006900 {
@@ -76,7 +82,7 @@ 
			interrupts = <0 35 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart1>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 1>;

		};



		serial2: serial@54006a00 {
@@ -86,7 +92,7 @@ 
			interrupts = <0 37 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart2>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 2>;

		};



		serial3: serial@54006b00 {
@@ -96,7 +102,7 @@ 
			interrupts = <0 177 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_uart3>;

			clocks = <&uart_clk>;

			clocks = <&peri_clk 3>;

		};



		system_bus: system-bus@58c00000 {
@@ -114,6 +120,34 @@ 
			reg = <0x59801000 0x400>;

		};



		mioctrl@59810000 {

			compatible = "socionext,uniphier-mioctrl",

				     "simple-mfd", "syscon";

			reg = <0x59810000 0x800>;



			mio_clk: clock {

				#clock-cells = <1>;

			};



			mio_rst: reset {

				#reset-cells = <1>;

			};

		};



		perictrl@59820000 {

			compatible = "socionext,uniphier-perictrl",

				     "simple-mfd", "syscon";

			reg = <0x59820000 0x200>;



			peri_clk: clock {

				#clock-cells = <1>;

			};



			peri_rst: reset {

				#reset-cells = <1>;

			};

		};



		timer@60000200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x60000200 0x20>;
@@ -137,13 +171,28 @@ 
		};



		soc-glue@5f800000 {

			compatible = "simple-mfd", "syscon";

			compatible = "socionext,uniphier-soc-glue",

				     "simple-mfd", "syscon";

			reg = <0x5f800000 0x2000>;



			pinctrl: pinctrl {

				/* specify compatible in each SoC DTSI */

			};

		};



		sysctrl@61840000 {

			compatible = "socionext,uniphier-sysctrl",

				     "simple-mfd", "syscon";

			reg = <0x61840000 0x4000>;



			sys_clk: clock {

				#clock-cells = <1>;

			};



			sys_rst: reset {

				#reset-cells = <1>;

			};

		};

	};

};

arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts→arch/arm/boot/dts/uniphier-ld4-ref.dts

+6 −5
Original line number Diff line number Diff line 
/*

 * Device Tree Source for UniPhier PH1-LD4 Reference Board

 * Device Tree Source for UniPhier LD4 Reference Board

 *

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual
@@ -43,13 +44,13 @@ 
 */



/dts-v1/;

/include/ "uniphier-ph1-ld4.dtsi"

/include/ "uniphier-ld4.dtsi"

/include/ "uniphier-ref-daughter.dtsi"

/include/ "uniphier-support-card.dtsi"



/ {

	model = "UniPhier PH1-LD4 Reference Board";

	compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4";

	model = "UniPhier LD4 Reference Board";

	compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4";



	memory {

		device_type = "memory";

arch/arm/boot/dts/uniphier-ph1-ld4.dtsi→arch/arm/boot/dts/uniphier-ld4.dtsi

+40 −19
Original line number Diff line number Diff line 
/*

 * Device Tree Source for UniPhier PH1-LD4 SoC

 * Device Tree Source for UniPhier LD4 SoC

 *

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual
@@ -45,7 +46,7 @@ 
/include/ "uniphier-common32.dtsi"



/ {

	compatible = "socionext,ph1-ld4";

	compatible = "socionext,uniphier-ld4";



	cpus {

		#address-cells = <1>;
@@ -55,6 +56,7 @@ 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

			enable-method = "psci";

			next-level-cache = <&l2>;

		};

	};
@@ -65,18 +67,6 @@ 
			compatible = "fixed-clock";

			clock-frequency = <50000000>;

		};



		uart_clk: uart_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <36864000>;

		};



		iobus_clk: iobus_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <100000000>;

		};

	};

};
@@ -101,7 +91,7 @@ 
		interrupts = <0 41 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c0>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 4>;

		clock-frequency = <100000>;

	};
@@ -114,7 +104,7 @@ 
		interrupts = <0 42 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c1>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 5>;

		clock-frequency = <100000>;

	};
@@ -127,7 +117,7 @@ 
		interrupts = <0 43 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c2>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 6>;

		clock-frequency = <400000>;

	};
@@ -140,7 +130,7 @@ 
		interrupts = <0 44 1>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_i2c3>;

		clocks = <&iobus_clk>;

		clocks = <&peri_clk 7>;

		clock-frequency = <100000>;

	};
@@ -151,6 +141,8 @@ 
		interrupts = <0 80 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb0>;

		clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;

		resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;

	};



	usb1: usb@5a810100 {
@@ -160,6 +152,8 @@ 
		interrupts = <0 81 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb1>;

		clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;

		resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;

	};



	usb2: usb@5a820100 {
@@ -169,6 +163,8 @@ 
		interrupts = <0 82 4>;

		pinctrl-names = "default";

		pinctrl-0 = <&pinctrl_usb2>;

		clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;

		resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;

	};



};
@@ -181,6 +177,31 @@ 
	interrupts = <0 29 4>;

};



&mio_clk {

	compatible = "socionext,uniphier-ld4-mio-clock";

};



&mio_rst {

	compatible = "socionext,uniphier-ld4-mio-reset";

	resets = <&sys_rst 7>;

};



&peri_clk {

	compatible = "socionext,uniphier-ld4-peri-clock";

};



&peri_rst {

	compatible = "socionext,uniphier-ld4-peri-reset";

};



&pinctrl {

	compatible = "socionext,uniphier-ld4-pinctrl";

};



&sys_clk {

	compatible = "socionext,uniphier-ld4-clock";

};



&sys_rst {

	compatible = "socionext,uniphier-ld4-reset";

};

arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts→arch/arm/boot/dts/uniphier-ld6b-ref.dts

+6 −5
Original line number Diff line number Diff line 
/*

 * Device Tree Source for UniPhier PH1-LD6b Reference Board

 * Device Tree Source for UniPhier LD6b Reference Board

 *

 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>

 * Copyright (C) 2015-2016 Socionext Inc.

 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

 *

 * This file is dual-licensed: you can use it either under the terms

 * of the GPL or the X11 license, at your option. Note that this dual
@@ -43,13 +44,13 @@ 
 */



/dts-v1/;

/include/ "uniphier-ph1-ld6b.dtsi"

/include/ "uniphier-ld6b.dtsi"

/include/ "uniphier-ref-daughter.dtsi"

/include/ "uniphier-support-card.dtsi"



/ {

	model = "UniPhier PH1-LD6b Reference Board";

	compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b";

	model = "UniPhier LD6b Reference Board";

	compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b";



	memory {

		device_type = "memory";