drm/amdgpu: add DMA implementation for si v8

struct amdgpu_sdma {

	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];

#ifdef CONFIG_DRM_AMDGPU_SI

	//SI DMA has a difference trap irq number for the second engine

	struct amdgpu_irq_src	trap_irq_1;

#endif

	struct amdgpu_irq_src	trap_irq;

	struct amdgpu_irq_src	illegal_inst_irq;

	int			num_instances;

/*

 * Copyright 2015 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __SI_DMA_H__

#define __SI_DMA_H__

extern const struct amd_ip_funcs si_dma_ip_funcs;

#endif

#define	HDP_NONSURFACE_INFO				0xB02

#define	HDP_NONSURFACE_SIZE				0xB03

#define HDP_DEBUG0  					0xBCC

#define HDP_ADDR_CONFIG  				0xBD2

#define HDP_MISC_CNTL					0xBD3

#define 	HDP_FLUSH_INVALIDATE_CACHE			(1 << 0)