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Commit 30a564be authored by Thomas Gleixner's avatar Thomas Gleixner Committed by H. Peter Anvin
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x86, hpet: Restrict read back to affected ATI chipsets 



After programming the HPET, we do a readback as a workaround for
ATI/SBx00 chipsets as a synchronization.  Unfortunately this triggers
an erratum in newer ICH chipsets (ICH9+) where reading the comparator
immediately after the write returns the old value.  Furthermore, as
always, I/O reads are bad for performance.

Therefore, restrict the readback to the chipsets that need it, or, for
debugging purposes, when we are running with hpet=verbose.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarVenkatesh Pallipadi <venki@google.com>
LKML-Reference: <20100225185348.GA9674@linux-os.sc.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 1d16b0f2

arch/x86/include/asm/hpet.h

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ extern unsigned long force_hpet_address; 
extern u8 hpet_blockid;

extern int hpet_force_user;

extern u8 hpet_msi_disable;

extern u8 hpet_readback_cmp;

extern int is_hpet_enabled(void);

extern int hpet_enable(void);

extern void hpet_disable(void);

arch/x86/kernel/hpet.c

+17 −12
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
unsigned long				hpet_address;

u8					hpet_blockid; /* OS timer block num */

u8					hpet_msi_disable;

u8					hpet_readback_cmp;



#ifdef CONFIG_PCI_MSI

static unsigned long			hpet_num_timers;
@@ -395,19 +396,23 @@ static int hpet_next_event(unsigned long delta, 
	 * at that point and we would wait for the next hpet interrupt

	 * forever. We found out that reading the CMP register back

	 * forces the transfer so we can rely on the comparison with

	 * the counter register below. If the read back from the

	 * compare register does not match the value we programmed

	 * then we might have a real hardware problem. We can not do

	 * much about it here, but at least alert the user/admin with

	 * a prominent warning.

	 * An erratum on some chipsets (ICH9,..), results in comparator read

	 * immediately following a write returning old value. Workaround

	 * for this is to read this value second time, when first

	 * read returns old value.

	 * the counter register below.

	 *

	 * That works fine on those ATI chipsets, but on newer Intel

	 * chipsets (ICH9...) this triggers due to an erratum: Reading

	 * the comparator immediately following a write is returning

	 * the old value.

	 *

	 * We restrict the read back to the affected ATI chipsets (set

	 * by quirks) and also run it with hpet=verbose for debugging

	 * purposes.

	 */

	if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {

		WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,

		  KERN_WARNING "hpet: compare register read back failed.\n");

	if (hpet_readback_cmp || hpet_verbose) {

		u32 cmp = hpet_readl(HPET_Tn_CMP(timer));



		if (cmp != cnt)

			printk_once(KERN_WARNING

			    "hpet: compare register read back failed.\n");

	}



	return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;

arch/x86/kernel/quirks.c

+5 −0
Original line number Diff line number Diff line
@@ -495,10 +495,15 @@ void force_hpet_resume(void) 
/*

 * HPET MSI on some boards (ATI SB700/SB800) has side effect on

 * floppy DMA. Disable HPET MSI on such platforms.

 *

 * Also force the read back of the CMP register in hpet_next_event()

 * to work around the problem that the CMP register write seems to be

 * delayed. See hpet_next_event() for details.

 */

static void force_disable_hpet_msi(struct pci_dev *unused)

{

	hpet_msi_disable = 1;

	hpet_readback_cmp = 1;

}



DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,