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Commit 30600823 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add system PM device binding for Lagoon"

parents a6352668 f1b68c75

bindings/interrupt-controller/qcom,pdc.txt

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ Properties: 
	Value type: <string>

	Definition: Should contain "qcom,<soc>-pdc"

		    - "qcom,sdm845-pdc": For SDM845

		    - "qcom,lagoon-pdc": For Lagoon



- reg:

	Usage: required

qcom/lagoon.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-lagoon.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>



/ {

	model = "Qualcomm Technologies, Inc. Lagoon";
@@ -685,6 +686,52 @@ 
		};

	};



	pdc: interrupt-controller@b220000 {

		compatible = "qcom,lagoon-pdc";

		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;

		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,

				  <126 657 12>, <138 139 15>;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

		interrupt-controller;

	};



	apps_rsc: rsc@18200000 {

		label = "apps_rsc";

		compatible = "qcom,rpmh-rsc";

		reg = <0x18200000 0x10000>,

		      <0x18210000 0x10000>,

		      <0x18220000 0x10000>;

		reg-names = "drv-0", "drv-1", "drv-2";

		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		qcom,tcs-offset = <0xd00>;

		qcom,drv-id = <2>;

		qcom,tcs-config = <ACTIVE_TCS  2>,

				  <SLEEP_TCS   3>,

				  <WAKE_TCS    3>,

				  <CONTROL_TCS 1>;



		system_pm {

			compatible = "qcom,system-pm";

		};

	};



	disp_rsc: rsc@af20000 {

		label = "disp_rsc";

		compatible = "qcom,rpmh-rsc";

		reg = <0xaf20000 0x10000>;

		reg-names = "drv-0";

		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;

		qcom,tcs-offset = <0x1c00>;

		qcom,drv-id = <0>;

		qcom,tcs-config = <ACTIVE_TCS  0>,

				  <SLEEP_TCS   1>,

				  <WAKE_TCS    1>,

				  <CONTROL_TCS 1>;

	};



	qcom,msm-imem@146ab000 {

		compatible = "qcom,msm-imem";

		reg = <0x146ab000 0x1000>;