pinctrl: add samsung pinctrl and gpiolib driver

Samsung GPIO and Pin Mux/Config controller

Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware

controller. It controls the input/output settings on the available pads/pins

and also provides ability to multiplex and configure the output of various

on-chip controllers onto these pads.

Required Properties:

- compatible: should be one of the following.

  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.

  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.

- reg: Base address of the pin controller hardware module and length of

  the address space it occupies.

- interrupts: interrupt specifier for the controller. The format and value of

  the interrupt specifier depends on the interrupt parent for the controller.

- Pin mux/config groups as child nodes: The pin mux (selecting pin function

  mode) and pin config (pull up/down, driver strength) settings are represented

  as child nodes of the pin-controller node. There should be atleast one

  child node and there is no limit on the count of these child nodes.

  The child node should contain a list of pin(s) on which a particular pin

  function selection or pin configuration (or both) have to applied. This

  list of pins is specified using the property name "samsung,pins". There

  should be atleast one pin specfied for this property and there is no upper

  limit on the count of pins that can be specified. The pins are specified

  using pin names which are derived from the hardware manual of the SoC. As

  an example, the pins in GPA0 bank of the pin controller can be represented

  as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.

  The format of the pin names should be (as per the hardware manual)

  "[pin bank name]-[pin number within the bank]".

  The pin function selection that should be applied on the pins listed in the

  child node is specified using the "samsung,pin-function" property. The value

  of this property that should be applied to each of the pins listed in the

  "samsung,pins" property should be picked from the hardware manual of the SoC

  for the specified pin group. This property is optional in the child node if

  no specific function selection is desired for the pins listed in the child

  node. The value of this property is used as-is to program the pin-controller

  function selector register of the pin-bank.

  The child node can also optionally specify one or more of the pin

  configuration that should be applied on all the pins listed in the

  "samsung,pins" property of the child node. The following pin configuration

  properties are supported.

  - samsung,pin-pud: Pull up/down configuration.

  - samsung,pin-drv: Drive strength configuration.

  - samsung,pin-pud-pdn: Pull up/down configuration in power down mode.

  - samsung,pin-drv-pdn: Drive strength configuration in power down mode.

  The values specified by these config properties should be derived from the

  hardware manual and these values are programmed as-is into the pin

  pull up/down and driver strength register of the pin-controller.

  Note: A child should include atleast a pin function selection property or

  pin configuration property (one or more) or both.

  The client nodes that require a particular pin function selection and/or

  pin configuration should use the bindings listed in the "pinctrl-bindings.txt"

  file.

External GPIO and Wakeup Interrupts:

The controller supports two types of external interrupts over gpio. The first

is the external gpio interrupt and second is the external wakeup interrupts.

The difference between the two is that the external wakeup interrupts can be

used as system wakeup events.

A. External GPIO Interrupts: For supporting external gpio interrupts, the

   following properties should be specified in the pin-controller device node.

- interrupt-controller: identifies the controller node as interrupt-parent.

- #interrupt-cells: the value of this property should be 2.

  - First Cell: represents the external gpio interrupt number local to the

    external gpio interrupt space of the controller.

  - Second Cell: flags to identify the type of the interrupt

    - 1 = rising edge triggered

    - 2 = falling edge triggered

    - 3 = rising and falling edge triggered

    - 4 = high level triggered

    - 8 = low level triggered

B. External Wakeup Interrupts: For supporting external wakeup interrupts, a

   child node representing the external wakeup interrupt controller should be

   included in the pin-controller device node. This child node should include

   the following properties.

   - compatible: identifies the type of the external wakeup interrupt controller

     The possible values are:

     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller

       found on Samsung Exynos4210 SoC.

   - interrupt-parent: phandle of the interrupt parent to which the external

     wakeup interrupts are forwarded to.

   - interrupt-controller: identifies the node as interrupt-parent.

   - #interrupt-cells: the value of this property should be 2

     - First Cell: represents the external wakeup interrupt number local to

       the external wakeup interrupt space of the controller.

     - Second Cell: flags to identify the type of the interrupt

       - 1 = rising edge triggered

       - 2 = falling edge triggered

       - 3 = rising and falling edge triggered

       - 4 = high level triggered

       - 8 = low level triggered

Aliases:

All the pin controller nodes should be represented in the aliases node using

the following format 'pinctrl{n}' where n is a unique number for the alias.

Example 1: A pin-controller node with pin groups.

	pinctrl_0: pinctrl@11400000 {

		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11400000 0x1000>;

		interrupts = <0 47 0>;

		uart0_data: uart0-data {

			samsung,pins = "gpa0-0", "gpa0-1";

			samsung,pin-function = <2>;

			samsung,pin-pud = <0>;

			samsung,pin-drv = <0>;

		};

		uart0_fctl: uart0-fctl {

			samsung,pins = "gpa0-2", "gpa0-3";

			samsung,pin-function = <2>;

			samsung,pin-pud = <0>;

			samsung,pin-drv = <0>;

		};

		uart1_data: uart1-data {

			samsung,pins = "gpa0-4", "gpa0-5";

			samsung,pin-function = <2>;

			samsung,pin-pud = <0>;

			samsung,pin-drv = <0>;

		};

		uart1_fctl: uart1-fctl {

			samsung,pins = "gpa0-6", "gpa0-7";

			samsung,pin-function = <2>;

			samsung,pin-pud = <0>;

			samsung,pin-drv = <0>;

		};

		i2c2_bus: i2c2-bus {

			samsung,pins = "gpa0-6", "gpa0-7";

			samsung,pin-function = <3>;

			samsung,pin-pud = <3>;

			samsung,pin-drv = <0>;

		};

	};

Example 2: A pin-controller node with external wakeup interrupt controller node.

	pinctrl_1: pinctrl@11000000 {

		compatible = "samsung,pinctrl-exynos4210";

		reg = <0x11000000 0x1000>;

		interrupts = <0 46 0>;

		interrupt-controller;

		#interrupt-cells = <2>;

		wakup_eint: wakeup-interrupt-controller {

			compatible = "samsung,exynos4210-wakeup-eint";

			interrupt-parent = <&gic>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,

					<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,

					<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,

					<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,

					<0 32 0>;

		};

	};

Example 3: A uart client node that supports 'default' and 'flow-control' states.

	uart@13800000 {

		compatible = "samsung,exynos4210-uart";

		reg = <0x13800000 0x100>;

		interrupts = <0 52 0>;

		pinctrl-names = "default", "flow-control;

		pinctrl-0 = <&uart0_data>;

		pinctrl-1 = <&uart0_data &uart0_fctl>;

	};

Example 4: Set up the default pin state for uart controller.

	static int s3c24xx_serial_probe(struct platform_device *pdev) {

		struct pinctrl *pinctrl;

		...

		...

		pinctrl = devm_pinctrl_get_select_default(&pdev->dev);

	}

	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7

	  ports of 8 GPIO pins each.

config PINCTRL_SAMSUNG

	bool "Samsung pinctrl driver"

	select PINMUX

	select PINCONF

source "drivers/pinctrl/spear/Kconfig"

endmenu

obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o

obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o

obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o

obj-$(CONFIG_PINCTRL_SAMSUNG)	+= pinctrl-samsung.o

obj-$(CONFIG_PLAT_SPEAR)	+= spear/

/*

 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.

 *

 * Copyright (c) 2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 * Copyright (c) 2012 Linaro Ltd

 *		http://www.linaro.org

 *

 * Author: Thomas Abraham <thomas.ab@samsung.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */

#ifndef __PINCTRL_SAMSUNG_H

#define __PINCTRL_SAMSUNG_H

#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>

#include <linux/pinctrl/pinconf.h>

#include <linux/pinctrl/consumer.h>

#include <linux/pinctrl/machine.h>

/* register offsets within a pin bank */

#define DAT_REG		0x4

#define PUD_REG		0x8

#define DRV_REG		0xC

#define CONPDN_REG	0x10

#define PUDPDN_REG	0x14

/* pinmux function number for pin as gpio output line */

#define FUNC_OUTPUT	0x1

/**

 * enum pincfg_type - possible pin configuration types supported.

 * @PINCFG_TYPE_PUD: Pull up/down configuration.

 * @PINCFG_TYPE_DRV: Drive strength configuration.

 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.

 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.

 */

enum pincfg_type {

	PINCFG_TYPE_PUD,

	PINCFG_TYPE_DRV,

	PINCFG_TYPE_CON_PDN,

	PINCFG_TYPE_PUD_PDN,

};

/*

 * pin configuration (pull up/down and drive strength) type and its value are

 * packed together into a 16-bits. The upper 8-bits represent the configuration

 * type and the lower 8-bits hold the value of the configuration type.

 */

#define PINCFG_TYPE_MASK		0xFF

#define PINCFG_VALUE_SHIFT		8

#define PINCFG_VALUE_MASK		(0xFF << PINCFG_VALUE_SHIFT)

#define PINCFG_PACK(type, value)	(((value) << PINCFG_VALUE_SHIFT) | type)

#define PINCFG_UNPACK_TYPE(cfg)		((cfg) & PINCFG_TYPE_MASK)

#define PINCFG_UNPACK_VALUE(cfg)	(((cfg) & PINCFG_VALUE_MASK) >> \

						PINCFG_VALUE_SHIFT)

/**

 * enum eint_type - possible external interrupt types.

 * @EINT_TYPE_NONE: bank does not support external interrupts

 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts

 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts

 *

 * Samsung GPIO controller groups all the available pins into banks. The pins

 * in a pin bank can support external gpio interrupts or external wakeup

 * interrupts or no interrupts at all. From a software perspective, the only

 * difference between external gpio and external wakeup interrupts is that

 * the wakeup interrupts can additionally wakeup the system if it is in

 * suspended state.

 */

enum eint_type {

	EINT_TYPE_NONE,

	EINT_TYPE_GPIO,

	EINT_TYPE_WKUP,

};

/* maximum length of a pin in pin descriptor (example: "gpa0-0") */

#define PIN_NAME_LENGTH	10

#define PIN_GROUP(n, p, f)				\

	{						\

		.name		= n,			\

		.pins		= p,			\

		.num_pins	= ARRAY_SIZE(p),	\

		.func		= f			\

	}

#define PMX_FUNC(n, g)					\

	{						\

		.name		= n,			\

		.groups		= g,			\

		.num_groups	= ARRAY_SIZE(g),	\

	}

struct samsung_pinctrl_drv_data;

/**

 * struct samsung_pin_bank: represent a controller pin-bank.

 * @reg_offset: starting offset of the pin-bank registers.

 * @pin_base: starting pin number of the bank.

 * @nr_pins: number of pins included in this bank.

 * @func_width: width of the function selector bit field.

 * @pud_width: width of the pin pull up/down selector bit field.

 * @drv_width: width of the pin driver strength selector bit field.

 * @conpdn_width: width of the sleep mode function selector bin field.

 * @pudpdn_width: width of the sleep mode pull up/down selector bit field.

 * @eint_type: type of the external interrupt supported by the bank.

 * @irq_base: starting controller local irq number of the bank.

 * @name: name to be prefixed for each pin in this pin bank.

 */

struct samsung_pin_bank {

	u32		pctl_offset;

	u32		pin_base;

	u8		nr_pins;

	u8		func_width;

	u8		pud_width;

	u8		drv_width;

	u8		conpdn_width;

	u8		pudpdn_width;

	enum eint_type	eint_type;

	u32		irq_base;

	char		*name;

};

/**

 * struct samsung_pin_ctrl: represent a pin controller.

 * @pin_banks: list of pin banks included in this controller.

 * @nr_banks: number of pin banks.

 * @base: starting system wide pin number.

 * @nr_pins: number of pins supported by the controller.

 * @nr_gint: number of external gpio interrupts supported.

 * @nr_wint: number of external wakeup interrupts supported.

 * @geint_con: offset of the ext-gpio controller registers.

 * @geint_mask: offset of the ext-gpio interrupt mask registers.

 * @geint_pend: offset of the ext-gpio interrupt pending registers.

 * @weint_con: offset of the ext-wakeup controller registers.

 * @weint_mask: offset of the ext-wakeup interrupt mask registers.

 * @weint_pend: offset of the ext-wakeup interrupt pending registers.

 * @svc: offset of the interrupt service register.

 * @eint_gpio_init: platform specific callback to setup the external gpio

 *	interrupts for the controller.

 * @eint_wkup_init: platform specific callback to setup the external wakeup

 *	interrupts for the controller.

 * @label: for debug information.

 */

struct samsung_pin_ctrl {

	struct samsung_pin_bank	*pin_banks;

	u32		nr_banks;

	u32		base;

	u32		nr_pins;

	u32		nr_gint;

	u32		nr_wint;

	u32		geint_con;

	u32		geint_mask;

	u32		geint_pend;

	u32		weint_con;

	u32		weint_mask;

	u32		weint_pend;

	u32		svc;

	int		(*eint_gpio_init)(struct samsung_pinctrl_drv_data *);

	int		(*eint_wkup_init)(struct samsung_pinctrl_drv_data *);

	char		*label;

};

/**

 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.

 * @virt_base: register base address of the controller.

 * @dev: device instance representing the controller.

 * @irq: interrpt number used by the controller to notify gpio interrupts.

 * @ctrl: pin controller instance managed by the driver.

 * @pctl: pin controller descriptor registered with the pinctrl subsystem.

 * @pctl_dev: cookie representing pinctrl device instance.

 * @pin_groups: list of pin groups available to the driver.

 * @nr_groups: number of such pin groups.

 * @pmx_functions: list of pin functions available to the driver.

 * @nr_function: number of such pin functions.

 * @gc: gpio_chip instance registered with gpiolib.

 * @grange: linux gpio pin range supported by this controller.

 */

struct samsung_pinctrl_drv_data {

	void __iomem			*virt_base;

	struct device			*dev;

	int				irq;

	struct samsung_pin_ctrl		*ctrl;

	struct pinctrl_desc		pctl;

	struct pinctrl_dev		*pctl_dev;

	const struct samsung_pin_group	*pin_groups;

	unsigned int			nr_groups;

	const struct samsung_pmx_func	*pmx_functions;

	unsigned int			nr_functions;

	struct irq_domain		*gpio_irqd;

	struct irq_domain		*wkup_irqd;

	struct gpio_chip		*gc;

	struct pinctrl_gpio_range	grange;

};

/**

 * struct samsung_pin_group: represent group of pins of a pinmux function.

 * @name: name of the pin group, used to lookup the group.

 * @pins: the pins included in this group.

 * @num_pins: number of pins included in this group.

 * @func: the function number to be programmed when selected.

 */

struct samsung_pin_group {

	const char		*name;

	const unsigned int	*pins;

	u8			num_pins;

	u8			func;

};

/**

 * struct samsung_pmx_func: represent a pin function.

 * @name: name of the pin function, used to lookup the function.

 * @groups: one or more names of pin groups that provide this function.

 * @num_groups: number of groups included in @groups.

 */

struct samsung_pmx_func {

	const char		*name;

	const char		**groups;

	u8			num_groups;

};

/* list of all exported SoC specific data */

extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];

#endif /* __PINCTRL_SAMSUNG_H */