Loading arch/x86/mm/pageattr-test.c +1 −3 Original line number Diff line number Diff line Loading @@ -16,14 +16,12 @@ enum { NTEST = 400, LOWEST_LEVEL = PG_LEVEL_4K, #ifdef CONFIG_X86_64 LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #elif defined(CONFIG_X86_PAE) LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #else LOWEST_LEVEL = 4, /* lookup_address lies here */ LPS = (1 << 22), #endif GPS = (1<<30) Loading arch/x86/mm/pageattr.c +6 −3 Original line number Diff line number Diff line Loading @@ -28,6 +28,8 @@ pte_t *lookup_address(unsigned long address, int *level) pud_t *pud; pmd_t *pmd; *level = PG_LEVEL_NONE; if (pgd_none(*pgd)) return NULL; pud = pud_offset(pgd, address); Loading @@ -36,11 +38,12 @@ pte_t *lookup_address(unsigned long address, int *level) pmd = pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; *level = 3; *level = PG_LEVEL_2M; if (pmd_large(*pmd)) return (pte_t *)pmd; *level = 4; *level = PG_LEVEL_4K; return pte_offset_kernel(pmd, address); } Loading Loading @@ -145,7 +148,7 @@ __change_page_attr(unsigned long address, struct page *page, pgprot_t prot) address < (unsigned long)&_etext && (pgprot_val(prot) & _PAGE_NX)); if (level == 4) { if (level == PG_LEVEL_4K) { set_pte_atomic(kpte, mk_pte(page, canon_pgprot(prot))); } else { err = split_large_page(kpte, address); Loading include/asm-x86/pgtable.h +6 −0 Original line number Diff line number Diff line Loading @@ -234,6 +234,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #ifndef __ASSEMBLY__ enum { PG_LEVEL_NONE, PG_LEVEL_4K, PG_LEVEL_2M, }; /* * Helper function that returns the kernel pagetable entry controlling * the virtual address 'address'. NULL means no pagetable entry present. Loading Loading
arch/x86/mm/pageattr-test.c +1 −3 Original line number Diff line number Diff line Loading @@ -16,14 +16,12 @@ enum { NTEST = 400, LOWEST_LEVEL = PG_LEVEL_4K, #ifdef CONFIG_X86_64 LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #elif defined(CONFIG_X86_PAE) LOWEST_LEVEL = 4, LPS = (1 << PMD_SHIFT), #else LOWEST_LEVEL = 4, /* lookup_address lies here */ LPS = (1 << 22), #endif GPS = (1<<30) Loading
arch/x86/mm/pageattr.c +6 −3 Original line number Diff line number Diff line Loading @@ -28,6 +28,8 @@ pte_t *lookup_address(unsigned long address, int *level) pud_t *pud; pmd_t *pmd; *level = PG_LEVEL_NONE; if (pgd_none(*pgd)) return NULL; pud = pud_offset(pgd, address); Loading @@ -36,11 +38,12 @@ pte_t *lookup_address(unsigned long address, int *level) pmd = pmd_offset(pud, address); if (pmd_none(*pmd)) return NULL; *level = 3; *level = PG_LEVEL_2M; if (pmd_large(*pmd)) return (pte_t *)pmd; *level = 4; *level = PG_LEVEL_4K; return pte_offset_kernel(pmd, address); } Loading Loading @@ -145,7 +148,7 @@ __change_page_attr(unsigned long address, struct page *page, pgprot_t prot) address < (unsigned long)&_etext && (pgprot_val(prot) & _PAGE_NX)); if (level == 4) { if (level == PG_LEVEL_4K) { set_pte_atomic(kpte, mk_pte(page, canon_pgprot(prot))); } else { err = split_large_page(kpte, address); Loading
include/asm-x86/pgtable.h +6 −0 Original line number Diff line number Diff line Loading @@ -234,6 +234,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) #ifndef __ASSEMBLY__ enum { PG_LEVEL_NONE, PG_LEVEL_4K, PG_LEVEL_2M, }; /* * Helper function that returns the kernel pagetable entry controlling * the virtual address 'address'. NULL means no pagetable entry present. Loading