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Commit 3020ca71 authored by Hans Verkuil's avatar Hans Verkuil Committed by Mauro Carvalho Chehab
Browse files

[media] v4l2-dv-timings.h: fix polarity for 4k formats 



The VSync polarity was negative instead of positive for the 4k CEA formats.
I probably copy-and-pasted these from the DMT 4k format, which does have a
negative VSync polarity.

Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Reported-by: default avatarMartin Bugge <marbugge@cisco.com>
Cc: <stable@vger.kernel.org>      # for v4.1 and up
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@osg.samsung.com>
parent 8bbb6568

include/uapi/linux/v4l2-dv-timings.h

+20 −10
Original line number Diff line number Diff line
@@ -183,7 +183,8 @@ 


#define V4L2_DV_BT_CEA_3840X2160P24 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -191,14 +192,16 @@ 


#define V4L2_DV_BT_CEA_3840X2160P25 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \

}



#define V4L2_DV_BT_CEA_3840X2160P30 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -206,14 +209,16 @@ 


#define V4L2_DV_BT_CEA_3840X2160P50 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \

}



#define V4L2_DV_BT_CEA_3840X2160P60 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -221,7 +226,8 @@ 


#define V4L2_DV_BT_CEA_4096X2160P24 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -229,14 +235,16 @@ 


#define V4L2_DV_BT_CEA_4096X2160P25 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \

}



#define V4L2_DV_BT_CEA_4096X2160P30 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -244,14 +252,16 @@ 


#define V4L2_DV_BT_CEA_4096X2160P50 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \

}



#define V4L2_DV_BT_CEA_4096X2160P60 { \

	.type = V4L2_DV_BT_656_1120, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \

	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \

		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \

		594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \

		V4L2_DV_BT_STD_CEA861, \

		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \