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Commit 2fb45757 authored by Prudhvi Yarlagadda's avatar Prudhvi Yarlagadda Committed by Gerrit - the friendly Code Review server
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msm: qcom-geni-se: Make DFS clock table specific to SE of QUP 



Make DFS clock table specific to SE of QUP instead of keeping
the table specific to QUP common node as the table varies based
on individual SE.
The issue observed is because the DFS root frequencies table
is currently maintained per QUP. This will cause problem as
the DFS root frquencies at hardware level are defined per
SE of QUP and we might end up configuring wrong root frequency
and divider value assuming the same the table for all SEs.

Change-Id: I84baa22eae8bc757603864be810258d6b3c9c35c
Signed-off-by: default avatarPrudhvi Yarlagadda <pyarlaga@codeaurora.org>
parent 506b4826

drivers/platform/msm/qcom-geni-se.c

+12 −16
Original line number Diff line number Diff line
@@ -69,8 +69,6 @@ struct bus_vectors { 
 * @bus_bw_set_noc:	Clock plan for DDR path.

 * @cur_bus_bw_idx:	Current index within the bus clock plan.

 * @cur_bus_bw_idx_noc:	Current index within the DDR path clock plan.

 * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl.

 * @clk_perf_tbl:	Table of clock frequency input to Serial Engine clock.

 * @log_ctx:		Logging context to hold the debug information.

 * @vectors:		Structure to store Master End and Slave End IDs for

			QUPv3 clock and DDR path bus BW request.
@@ -107,8 +105,6 @@ struct geni_se_device { 
	unsigned long *bus_bw_set_noc;

	int cur_bus_bw_idx;

	int cur_bus_bw_idx_noc;

	unsigned int num_clk_levels;

	unsigned long *clk_perf_tbl;

	void *log_ctx;

	struct bus_vectors *vectors;

	int num_paths;
@@ -1135,31 +1131,31 @@ int geni_se_clk_tbl_get(struct se_geni_rsc *rsc, unsigned long **tbl) 
	mutex_lock(&geni_se_dev->geni_dev_lock);

	*tbl = NULL;



	if (geni_se_dev->clk_perf_tbl) {

		*tbl = geni_se_dev->clk_perf_tbl;

		ret = geni_se_dev->num_clk_levels;

	if (rsc->clk_perf_tbl) {

		*tbl = rsc->clk_perf_tbl;

		ret = rsc->num_clk_levels;

		goto exit_se_clk_tbl_get;

	}



	geni_se_dev->clk_perf_tbl = kzalloc(sizeof(*geni_se_dev->clk_perf_tbl) *

	rsc->clk_perf_tbl = kzalloc(sizeof(*rsc->clk_perf_tbl) *

						MAX_CLK_PERF_LEVEL, GFP_KERNEL);

	if (!geni_se_dev->clk_perf_tbl) {

	if (!rsc->clk_perf_tbl) {

		ret = -ENOMEM;

		goto exit_se_clk_tbl_get;

	}



	for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {

		geni_se_dev->clk_perf_tbl[i] = clk_round_rate(rsc->se_clk,

		rsc->clk_perf_tbl[i] = clk_round_rate(rsc->se_clk,

								prev_freq + 1);

		if (geni_se_dev->clk_perf_tbl[i] == prev_freq) {

			geni_se_dev->clk_perf_tbl[i] = 0;

		if (rsc->clk_perf_tbl[i] == prev_freq) {

			rsc->clk_perf_tbl[i] = 0;

			break;

		}

		prev_freq = geni_se_dev->clk_perf_tbl[i];

		prev_freq = rsc->clk_perf_tbl[i];

	}

	geni_se_dev->num_clk_levels = i;

	*tbl = geni_se_dev->clk_perf_tbl;

	ret = geni_se_dev->num_clk_levels;

	rsc->num_clk_levels = i;

	*tbl = rsc->clk_perf_tbl;

	ret = rsc->num_clk_levels;

exit_se_clk_tbl_get:

	mutex_unlock(&geni_se_dev->geni_dev_lock);

	return ret;

include/linux/qcom-geni-se.h

+5 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _LINUX_QCOM_GENI_SE
@@ -50,6 +50,8 @@ enum se_protocol_types { 
 * @geni_pinctrl:	Handle to the pinctrl configuration.

 * @geni_gpio_active:	Handle to the default/active pinctrl state.

 * @geni_gpi_sleep:	Handle to the sleep pinctrl state.

 * @num_clk_levels:	Number of valid clock levels in clk_perf_tbl.

 * @clk_perf_tbl:	Table of clock frequency input to Serial Engine clock.

 */

struct se_geni_rsc {

	struct device *ctrl_dev;
@@ -69,6 +71,8 @@ struct se_geni_rsc { 
	struct pinctrl_state *geni_gpio_active;

	struct pinctrl_state *geni_gpio_sleep;

	int	clk_freq_out;

	unsigned int num_clk_levels;

	unsigned long *clk_perf_tbl;

};



#define PINCTRL_DEFAULT	"default"