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Commit 2faae9fd authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
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msm: kgsl: Add FAL10 feature support for A650 



FAL10 is a power saving feature for DDR subsystem. It introduces a latency
in DDR memory accesses. Hence GPU will veto its participation.

Change-Id: I55702cf4532101564cf2cbe01df651a2bf284ede
Signed-off-by: default avatarMohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
parent 03b45949

drivers/gpu/msm/a6xx_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -1016,6 +1016,8 @@ 
/* LM registers */

#define A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD       0x1F94D



/* FAL10 veto register */

#define A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF         0x1F8F0



#define A6XX_GMU_AO_INTERRUPT_EN		0x23B03

#define A6XX_GMU_AO_HOST_INTERRUPT_CLR		0x23B04

drivers/gpu/msm/adreno-gpulist.h

+2 −0
Original line number Diff line number Diff line
@@ -960,6 +960,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
	.hwcg_count = ARRAY_SIZE(a620_hwcg_regs),

	.vbif = a650_gbif_regs,

	.vbif_count = ARRAY_SIZE(a650_gbif_regs),

	.veto_fal10 = true,

};



static const struct adreno_reglist a640_hwcg_regs[] = {
@@ -1121,6 +1122,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
	.zap_name = "a650_zap",

	.vbif = a650_gbif_regs,

	.vbif_count = ARRAY_SIZE(a650_gbif_regs),

	.veto_fal10 = true,

};



static const struct adreno_a6xx_core adreno_gpu_core_a680 = {

drivers/gpu/msm/adreno_a6xx.h

+2 −0
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@ struct adreno_a6xx_core { 
	const struct adreno_reglist *vbif;

	/** @vbif_count: Number of registers in @vbif */

	u32 vbif_count;

	/** @veto_fal10: veto status for fal10 feature */

	bool veto_fal10;

};



#define CP_CLUSTER_FE		0x0

drivers/gpu/msm/adreno_a6xx_gmu.c

+5 −0
Original line number Diff line number Diff line
@@ -960,10 +960,15 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, 
{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct gmu_device *gmu = KGSL_GMU_DEVICE(device);

	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);

	uint32_t gmu_log_info;

	int ret;

	unsigned int chipid = 0;



	/* Vote veto for FAL10 feature if supported*/

	if (a6xx_core->veto_fal10)

		gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 0x1);



	switch (boot_state) {

	case GMU_COLD_BOOT:

		/* Turn on TCM retention */