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Commit 2f3fd67a authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: Use MACROS instead of dm_logger 



Created MACROS for all log levels. Also Replaced
usage of dm_logger_write to the defined MACROS

Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 44c6f2e5

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

+1 −1
Original line number Diff line number Diff line
@@ -3079,7 +3079,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info( 
					    opm_object,

					    &ext_display_connection_info_tbl) != BP_RESULT_OK) {



		dm_logger_write(bp->base.ctx->logger, LOG_WARNING,

		DC_LOG_WARNING(bp->base.ctx->logger,

				"%s: Failed to read Connection Info Table", __func__);

		return BP_RESULT_UNSUPPORTED;

	}

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

+3 −3
Original line number Diff line number Diff line
@@ -239,7 +239,7 @@ static enum bp_result transmitter_control_v1_6( 
	if (cntl->action == TRANSMITTER_CONTROL_ENABLE ||

		cntl->action == TRANSMITTER_CONTROL_ACTIAVATE ||

		cntl->action == TRANSMITTER_CONTROL_DEACTIVATE) {

		dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\

		DC_LOG_BIOS(bp->base.ctx->logger, \

		"%s:ps.param.symclk_10khz = %d\n",\

		__func__, ps.param.symclk_10khz);

	}
@@ -331,7 +331,7 @@ static enum bp_result set_pixel_clock_v7( 
			(uint8_t) bp->cmd_helper->

				transmitter_color_depth_to_atom(

					bp_params->color_depth);

		dm_logger_write(bp->base.ctx->logger, LOG_BIOS,\

		DC_LOG_BIOS(bp->base.ctx->logger, \

				"%s:program display clock = %d"\

				"colorDepth = %d\n", __func__,\

				bp_params->target_pixel_clock, bp_params->color_depth);
@@ -772,7 +772,7 @@ static enum bp_result set_dce_clock_v2_1( 
		 */

		params.param.dceclk_10khz = cpu_to_le32(

				bp_params->target_clock_frequency / 10);

	dm_logger_write(bp->base.ctx->logger, LOG_BIOS,

	DC_LOG_BIOS(bp->base.ctx->logger,

			"%s:target_clock_frequency = %d"\

			"clock_type = %d \n", __func__,\

			bp_params->target_clock_frequency,\

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

+3 −3
Original line number Diff line number Diff line
@@ -1242,7 +1242,7 @@ unsigned int dcn_find_dcfclk_suits_all( 
	else

		dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;



	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,

	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

		"\tdcf_clk for voltage = %d\n", dcf_clk);

	return dcf_clk;

}
@@ -1441,7 +1441,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) 
void dcn_bw_sync_calcs_and_dml(struct dc *dc)

{

	kernel_fpu_begin();

	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,

	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"sr_exit_time: %d ns\n"

			"sr_enter_plus_exit_time: %d ns\n"

			"urgent_latency: %d ns\n"
@@ -1510,7 +1510,7 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc) 
			dc->dcn_soc->vmm_page_size,

			dc->dcn_soc->dram_clock_change_latency * 1000,

			dc->dcn_soc->return_bus_width);

	dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,

	DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,

			"rob_buffer_size_in_kbyte: %d\n"

			"det_buffer_size_in_kbyte: %d\n"

			"dpp_output_buffer_pixels: %d\n"

drivers/gpu/drm/amd/display/dc/core/dc.c

+4 −4
Original line number Diff line number Diff line
@@ -264,7 +264,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, 
	/* Only call if supported */

	if (tg->funcs->configure_crc)

		return tg->funcs->configure_crc(tg, &param);

	dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");

	DC_LOG_WARNING(dc->ctx->logger,  "CRC capture not supported.");

	return false;

}
@@ -297,7 +297,7 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, 


	if (tg->funcs->get_crc)

		return tg->funcs->get_crc(tg, r_cr, g_y, b_cb);

	dm_logger_write(dc->ctx->logger, LOG_WARNING, "CRC capture not supported.");

	DC_LOG_WARNING(dc->ctx->logger,  "CRC capture not supported.");

	return false;

}
@@ -618,7 +618,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) 


	dc->config = init_params->flags;



	dm_logger_write(dc->ctx->logger, LOG_DC,

	DC_LOG_DC(dc->ctx->logger,

			"Display Core initialized\n");
@@ -888,7 +888,7 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context) 
	if (false == context_changed(dc, context))

		return DC_OK;



	dm_logger_write(dc->ctx->logger, LOG_DC, "%s: %d streams\n",

	DC_LOG_DC(dc->ctx->logger,  "%s: %d streams\n",

				__func__, context->stream_count);



	for (i = 0; i < context->stream_count; i++) {

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+16 −16
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
#include "dce/dce_11_0_sh_mask.h"



#define LINK_INFO(...) \

	dm_logger_write(dc_ctx->logger, LOG_HW_HOTPLUG, \

	DC_LOG_HW_HOTPLUG(dc_ctx->logger,  \

		__VA_ARGS__)



/*******************************************************************************
@@ -677,11 +677,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 


		switch (edid_status) {

		case EDID_BAD_CHECKSUM:

			dm_logger_write(link->ctx->logger, LOG_ERROR,

			DC_LOG_ERROR(link->ctx->logger,

				"EDID checksum invalid.\n");

			break;

		case EDID_NO_RESPONSE:

			dm_logger_write(link->ctx->logger, LOG_ERROR,

			DC_LOG_ERROR(link->ctx->logger,

				"No EDID read.\n");

		default:

			break;
@@ -712,7 +712,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
					"%s: [Block %d] ", sink->edid_caps.display_name, i);

		}



		dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,

		DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,

			"%s: "

			"manufacturer_id = %X, "

			"product_id = %X, "
@@ -733,7 +733,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 
			sink->edid_caps.audio_mode_count);



		for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {

			dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER,

			DC_LOG_DETECTION_EDID_PARSER(link->ctx->logger,

				"%s: mode number = %d, "

				"format_code = %d, "

				"channel_count = %d, "
@@ -984,7 +984,7 @@ static bool construct( 
		}

		break;

	default:

		dm_logger_write(dc_ctx->logger, LOG_WARNING,

		DC_LOG_WARNING(dc_ctx->logger,

			"Unsupported Connector type:%d!\n", link->link_id.id);

		goto create_fail;

	}
@@ -1175,7 +1175,7 @@ static void dpcd_configure_panel_mode( 
			ASSERT(result == DDC_RESULT_SUCESSFULL);

		}

	}

	dm_logger_write(link->ctx->logger, LOG_DETECTION_DP_CAPS,

	DC_LOG_DETECTION_DP_CAPS(link->ctx->logger,

			"Link: %d eDP panel mode supported: %d "

			"eDP panel mode enabled: %d \n",

			link->link_index,
@@ -1965,7 +1965,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, 


	use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);



	dm_logger_write(link->ctx->logger, LOG_BACKLIGHT,

	DC_LOG_BACKLIGHT(link->ctx->logger,

			"New Backlight level: %d (0x%X)\n", level, level);



	if (dc_is_embedded_signal(link->connector_signal)) {
@@ -2150,20 +2150,20 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) 
					link, pipe_ctx->stream_res.stream_enc, &proposed_table);

	}

	else

		dm_logger_write(link->ctx->logger, LOG_WARNING,

		DC_LOG_WARNING(link->ctx->logger,

				"Failed to update"

				"MST allocation table for"

				"pipe idx:%d\n",

				pipe_ctx->pipe_idx);



	dm_logger_write(link->ctx->logger, LOG_MST,

	DC_LOG_MST(link->ctx->logger,

			"%s  "

			"stream_count: %d: \n ",

			__func__,

			link->mst_stream_alloc_table.stream_count);



	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {

		dm_logger_write(link->ctx->logger, LOG_MST,

		DC_LOG_MST(link->ctx->logger,

		"stream_enc[%d]: 0x%x      "

		"stream[%d].vcp_id: %d      "

		"stream[%d].slot_count: %d\n",
@@ -2240,7 +2240,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 
				link, pipe_ctx->stream_res.stream_enc, &proposed_table);

		}

		else {

				dm_logger_write(link->ctx->logger, LOG_WARNING,

				DC_LOG_WARNING(link->ctx->logger,

						"Failed to update"

						"MST allocation table for"

						"pipe idx:%d\n",
@@ -2248,14 +2248,14 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 
		}

	}



	dm_logger_write(link->ctx->logger, LOG_MST,

	DC_LOG_MST(link->ctx->logger,

			"%s"

			"stream_count: %d: ",

			__func__,

			link->mst_stream_alloc_table.stream_count);



	for (i = 0; i < MAX_CONTROLLER_NUM; i++) {

		dm_logger_write(link->ctx->logger, LOG_MST,

		DC_LOG_MST(link->ctx->logger,

		"stream_enc[%d]: 0x%x      "

		"stream[%d].vcp_id: %d      "

		"stream[%d].slot_count: %d\n",
@@ -2307,8 +2307,8 @@ void core_link_enable_stream( 
	status = enable_link(state, pipe_ctx);



	if (status != DC_OK) {

			dm_logger_write(pipe_ctx->stream->ctx->logger,

			LOG_WARNING, "enabling link %u failed: %d\n",

			DC_LOG_WARNING(pipe_ctx->stream->ctx->logger,

			 "enabling link %u failed: %d\n",

			pipe_ctx->stream->sink->link->link_index,

			status);