Merge tag 'drm-for-v4.12' of git://people.freedesktop.org/~airlied/linux

/* Fixed header pattern */

/* Fixed header pattern */

header:		.byte	0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00

header:		.byte	0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00

mfg_id:		.word	swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))

mfg_id:		.hword	swap16(mfgname2id(MFG_LNX1, MFG_LNX2, MFG_LNX3))

prod_code:	.word	0

prod_code:	.hword	0

/* Serial number. 32 bits, little endian. */

/* Serial number. 32 bits, little endian. */

serial_number:	.long	SERIAL

serial_number:	.long	SERIAL

descriptor1:

descriptor1:

/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */

/* Pixel clock in 10 kHz units. (0.-655.35 MHz, little-endian) */

clock:		.word	CLOCK/10

clock:		.hword	CLOCK/10

/* Horizontal active pixels 8 lsbits (0-4095) */

/* Horizontal active pixels 8 lsbits (0-4095) */

x_act_lsb:	.byte	XPIX&0xff

x_act_lsb:	.byte	XPIX&0xff

Amlogic specific extensions to the Synopsys Designware HDMI Controller

======================================================================

The Amlogic Meson Synopsys Designware Integration is composed of :

- A Synopsys DesignWare HDMI Controller IP

- A TOP control block controlling the Clocks and PHY

- A custom HDMI PHY in order to convert video to TMDS signal

 ___________________________________

|            HDMI TOP               |<= HPD

|___________________________________|

|                  |                |

|  Synopsys HDMI   |   HDMI PHY     |=> TMDS

|    Controller    |________________|

|___________________________________|<=> DDC

The HDMI TOP block only supports HPD sensing.

The Synopsys HDMI Controller interrupt is routed through the

TOP Block interrupt.

Communication to the TOP Block and the Synopsys HDMI Controller is done

via a pair of dedicated addr+read/write registers.

The HDMI PHY is configured by registers in the HHI register block.

Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux

selects either the ENCI encoder for the 576i or 480i formats or the ENCP

encoder for all the other formats including interlaced HD formats.

The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate

DVI timings for the HDMI controller.

Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare

HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF

audio source interfaces.

Required properties:

- compatible: value should be different for each SoC family as :

	- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"

	- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"

	- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"

	followed by the common "amlogic,meson-gx-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  and the Amlogic Meson venci clocks as described in

  Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"

- resets, resets-names: must have the phandles to the HDMI apb, glue and phy

  resets as described in :

  Documentation/devicetree/bindings/reset/reset.txt,

  the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"

Required nodes:

The connections to the HDMI ports are modeled using the OF graph

bindings specified in Documentation/devicetree/bindings/graph.txt.

The following table lists for each supported model the port number

corresponding to each HDMI output and input.

		Port 0		Port 1

-----------------------------------------

 S905 (GXBB)	VENC Input	TMDS Output

 S905X (GXL)	VENC Input	TMDS Output

 S905D (GXL)	VENC Input	TMDS Output

 S912 (GXM)	VENC Input	TMDS Output

Example:

hdmi-connector {

	compatible = "hdmi-connector";

	type = "a";

	port {

		hdmi_connector_in: endpoint {

			remote-endpoint = <&hdmi_tx_tmds_out>;

		};

	};

};

hdmi_tx: hdmi-tx@c883a000 {

	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";

	reg = <0x0 0xc883a000 0x0 0x1c>;

	interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;

	resets = <&reset RESET_HDMITX_CAPB3>,

		 <&reset RESET_HDMI_SYSTEM_RESET>,

		 <&reset RESET_HDMI_TX>;

	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";

	clocks = <&clkc CLKID_HDMI_PCLK>,

		 <&clkc CLKID_CLK81>,

		 <&clkc CLKID_GCLK_VENCI_INT0>;

	clock-names = "isfr", "iahb", "venci";

	#address-cells = <1>;

	#size-cells = <0>;

	/* VPU VENC Input */

	hdmi_tx_venc_port: port@0 {

		reg = <0>;

		hdmi_tx_in: endpoint {

			remote-endpoint = <&hdmi_tx_out>;

		};

	};

	/* TMDS Output */

	hdmi_tx_tmds_port: port@1 {

		reg = <1>;

		hdmi_tx_tmds_out: endpoint {

			remote-endpoint = <&hdmi_connector_in>;

		};

	};

};

- hpd-gpios:	The GPIO pin for HDMI hotplug detect (if it doesn't appear

- hpd-gpios:	The GPIO pin for HDMI hotplug detect (if it doesn't appear

		  as an interrupt/status bit in the HDMI controller

		  as an interrupt/status bit in the HDMI controller

		  itself).  See bindings/pinctrl/brcm,bcm2835-gpio.txt

		  itself).  See bindings/pinctrl/brcm,bcm2835-gpio.txt

- dmas:		Should contain one entry pointing to the DMA channel used to

		transfer audio data

- dma-names:	Should contain "audio-rx"

Required properties for DPI:

Required properties for DPI:

- compatible:	Should be "brcm,bcm2835-dpi"

- compatible:	Should be "brcm,bcm2835-dpi"

Parallel to LVDS Encoder

------------------------

This binding supports the parallel to LVDS encoders that don't require any

configuration.

LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple

incompatible data link layers have been used over time to transmit image data

to LVDS panels. This binding targets devices compatible with the following

specifications only.

[JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February

1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)

[LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National

Semiconductor

[VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video

Electronics Standards Association (VESA)

Those devices have been marketed under the FPD-Link and FlatLink brand names

among others.

Required properties:

- compatible: Must be "lvds-encoder"

Required nodes:

This device has two video ports. Their connections are modeled using the OF

graph bindings specified in Documentation/devicetree/bindings/graph.txt.

- Video port 0 for parallel input

- Video port 1 for LVDS output

Example

-------

lvds-encoder {

	compatible = "lvds-encoder";

	#address-cells = <1>;

	#size-cells = <0>;

	ports {

		#address-cells = <1>;

		#size-cells = <0>;

		port@0 {

			reg = <0>;

			lvds_enc_in: endpoint {

				remote-endpoint = <&display_out_rgb>;

			};

		};

		port@1 {

			reg = <1>;

			lvds_enc_out: endpoint {

				remote-endpoint = <&lvds_panel_in>;

			};

		};

	};

};

Drivers for the second video output of the GE B850v3:

   STDP4028-ge-b850v3-fw bridges (LVDS-DP)

   STDP2690-ge-b850v3-fw bridges (DP-DP++)

The video processing pipeline on the second output on the GE B850v3:

   Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output

Each bridge has a dedicated flash containing firmware for supporting the custom

design. The result is that, in this design, neither the STDP4028 nor the

STDP2690 behave as the stock bridges would. The compatible strings include the

suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with

the firmware specific for the GE B850v3.

The hardware do not provide control over the video processing pipeline, as the

two bridges behaves as a single one. The only interfaces exposed by the

hardware are EDID, HPD, and interrupts.

stdp4028-ge-b850v3-fw required properties:

  - compatible : "megachips,stdp4028-ge-b850v3-fw"

  - reg : I2C bus address

  - interrupt-parent : phandle of the interrupt controller that services

    interrupts to the device

  - interrupts : one interrupt should be described here, as in

    <0 IRQ_TYPE_LEVEL_HIGH>

  - ports : One input port(reg = <0>) and one output port(reg = <1>)

stdp2690-ge-b850v3-fw required properties:

    compatible : "megachips,stdp2690-ge-b850v3-fw"

  - reg : I2C bus address

  - ports : One input port(reg = <0>) and one output port(reg = <1>)

Example:

&mux2_i2c2 {

	status = "okay";

	clock-frequency = <100000>;

	stdp4028@73 {

		compatible = "megachips,stdp4028-ge-b850v3-fw";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x73>;

		interrupt-parent = <&gpio2>;

		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				stdp4028_in: endpoint {

					remote-endpoint = <&lvds0_out>;

				};

			};

			port@1 {

				reg = <1>;

				stdp4028_out: endpoint {

					remote-endpoint = <&stdp2690_in>;

				};

			};

		};

	};

	stdp2690@72 {

		compatible = "megachips,stdp2690-ge-b850v3-fw";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x72>;

		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				stdp2690_in: endpoint {

					remote-endpoint = <&stdp4028_out>;

				};

			};

			port@1 {

				reg = <1>;

				stdp2690_out: endpoint {

					/* Connector for external display */

				};

			};

		};

	};

};