Loading drivers/watchdog/aspeed_wdt.c +6 −3 Original line number Diff line number Diff line Loading @@ -232,11 +232,14 @@ static int aspeed_wdt_probe(struct platform_device *pdev) wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; } else { if (!strcmp(reset_type, "cpu")) wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU; wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | WDT_CTRL_RESET_SYSTEM; else if (!strcmp(reset_type, "soc")) wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC; wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; else if (!strcmp(reset_type, "system")) wdt->ctrl |= WDT_CTRL_RESET_SYSTEM; wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | WDT_CTRL_RESET_SYSTEM; else if (strcmp(reset_type, "none")) return -EINVAL; } Loading drivers/watchdog/dw_wdt.c +24 −8 Original line number Diff line number Diff line Loading @@ -34,6 +34,7 @@ #define WDOG_CONTROL_REG_OFFSET 0x00 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 Loading @@ -56,6 +57,9 @@ struct dw_wdt { unsigned long rate; struct watchdog_device wdd; struct reset_control *rst; /* Save/restore */ u32 control; u32 timeout; }; #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) Loading Loading @@ -121,14 +125,23 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) return 0; } static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) { u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); /* Disable interrupt mode; always perform system reset. */ val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; /* Enable watchdog. */ val |= WDOG_CONTROL_REG_WDT_EN_MASK; writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); } static int dw_wdt_start(struct watchdog_device *wdd) { struct dw_wdt *dw_wdt = to_dw_wdt(wdd); dw_wdt_set_timeout(wdd, wdd->timeout); writel(WDOG_CONTROL_REG_WDT_EN_MASK, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_arm_system_reset(dw_wdt); return 0; } Loading @@ -152,16 +165,13 @@ static int dw_wdt_restart(struct watchdog_device *wdd, unsigned long action, void *data) { struct dw_wdt *dw_wdt = to_dw_wdt(wdd); u32 val; writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); if (val & WDOG_CONTROL_REG_WDT_EN_MASK) if (dw_wdt_is_enabled(dw_wdt)) writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); else writel(WDOG_CONTROL_REG_WDT_EN_MASK, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_arm_system_reset(dw_wdt); /* wait for reset to assert... */ mdelay(500); Loading Loading @@ -198,6 +208,9 @@ static int dw_wdt_suspend(struct device *dev) { struct dw_wdt *dw_wdt = dev_get_drvdata(dev); dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); clk_disable_unprepare(dw_wdt->clk); return 0; Loading @@ -211,6 +224,9 @@ static int dw_wdt_resume(struct device *dev) if (err) return err; writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_ping(&dw_wdt->wdd); return 0; Loading drivers/watchdog/sprd_wdt.c +3 −1 Original line number Diff line number Diff line Loading @@ -154,8 +154,10 @@ static int sprd_wdt_enable(struct sprd_wdt *wdt) if (ret) return ret; ret = clk_prepare_enable(wdt->rtc_enable); if (ret) if (ret) { clk_disable_unprepare(wdt->enable); return ret; } sprd_wdt_unlock(wdt->base); val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); Loading Loading
drivers/watchdog/aspeed_wdt.c +6 −3 Original line number Diff line number Diff line Loading @@ -232,11 +232,14 @@ static int aspeed_wdt_probe(struct platform_device *pdev) wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; } else { if (!strcmp(reset_type, "cpu")) wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU; wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU | WDT_CTRL_RESET_SYSTEM; else if (!strcmp(reset_type, "soc")) wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC; wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM; else if (!strcmp(reset_type, "system")) wdt->ctrl |= WDT_CTRL_RESET_SYSTEM; wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP | WDT_CTRL_RESET_SYSTEM; else if (strcmp(reset_type, "none")) return -EINVAL; } Loading
drivers/watchdog/dw_wdt.c +24 −8 Original line number Diff line number Diff line Loading @@ -34,6 +34,7 @@ #define WDOG_CONTROL_REG_OFFSET 0x00 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 #define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 Loading @@ -56,6 +57,9 @@ struct dw_wdt { unsigned long rate; struct watchdog_device wdd; struct reset_control *rst; /* Save/restore */ u32 control; u32 timeout; }; #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd) Loading Loading @@ -121,14 +125,23 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s) return 0; } static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt) { u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); /* Disable interrupt mode; always perform system reset. */ val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; /* Enable watchdog. */ val |= WDOG_CONTROL_REG_WDT_EN_MASK; writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); } static int dw_wdt_start(struct watchdog_device *wdd) { struct dw_wdt *dw_wdt = to_dw_wdt(wdd); dw_wdt_set_timeout(wdd, wdd->timeout); writel(WDOG_CONTROL_REG_WDT_EN_MASK, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_arm_system_reset(dw_wdt); return 0; } Loading @@ -152,16 +165,13 @@ static int dw_wdt_restart(struct watchdog_device *wdd, unsigned long action, void *data) { struct dw_wdt *dw_wdt = to_dw_wdt(wdd); u32 val; writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); if (val & WDOG_CONTROL_REG_WDT_EN_MASK) if (dw_wdt_is_enabled(dw_wdt)) writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET); else writel(WDOG_CONTROL_REG_WDT_EN_MASK, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_arm_system_reset(dw_wdt); /* wait for reset to assert... */ mdelay(500); Loading Loading @@ -198,6 +208,9 @@ static int dw_wdt_suspend(struct device *dev) { struct dw_wdt *dw_wdt = dev_get_drvdata(dev); dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); clk_disable_unprepare(dw_wdt->clk); return 0; Loading @@ -211,6 +224,9 @@ static int dw_wdt_resume(struct device *dev) if (err) return err; writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt_ping(&dw_wdt->wdd); return 0; Loading
drivers/watchdog/sprd_wdt.c +3 −1 Original line number Diff line number Diff line Loading @@ -154,8 +154,10 @@ static int sprd_wdt_enable(struct sprd_wdt *wdt) if (ret) return ret; ret = clk_prepare_enable(wdt->rtc_enable); if (ret) if (ret) { clk_disable_unprepare(wdt->enable); return ret; } sprd_wdt_unlock(wdt->base); val = readl_relaxed(wdt->base + SPRD_WDT_CTRL); Loading