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Commit 2deeb495 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'cxgb4-collect-hardware-logs-via-ethtool' 



Rahul Lakkireddy says:

====================
cxgb4: collect hardware logs via ethtool

Collect more hardware logs via ethtool --get-dump facility.

Patch 1 collects on-chip memory layout information.

Patch 2 collects on-chip MC memory dumps.

Patch 3 collects HMA memory dump.

Patch 4 evaluates and skips TX and RX payload regions in memory dumps.

Patch 5 collects egress and ingress SGE queue contexts.

Patch 6 collects PCIe configuration logs
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 62fd8b18 6078ab19

drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

+68 −8
Original line number Diff line number Diff line
@@ -18,17 +18,15 @@ 
#ifndef __CUDBG_ENTITY_H__

#define __CUDBG_ENTITY_H__



#define EDC0_FLAG 3

#define EDC1_FLAG 4

#define EDC0_FLAG 0

#define EDC1_FLAG 1

#define MC_FLAG 2

#define MC0_FLAG 3

#define MC1_FLAG 4

#define HMA_FLAG 5



#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001



struct card_mem {

	u16 size_edc0;

	u16 size_edc1;

	u16 mem_flag;

};



struct cudbg_mbox_log {

	struct mbox_cmd entry;

	u32 hi[MBOX_LEN / 8];
@@ -87,6 +85,48 @@ struct cudbg_tp_la { 
	u8 data[0];

};



static const char * const cudbg_region[] = {

	"DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",

	"Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",

	"Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",

	"TDDP region:", "TPT region:", "STAG region:", "RQ region:",

	"RQUDP region:", "PBL region:", "TXPBL region:",

	"DBVFIFO region:", "ULPRX state:", "ULPTX state:",

	"On-chip queues:"

};



/* Memory region info relative to current memory (i.e. wrt 0). */

struct cudbg_region_info {

	bool exist; /* Does region exists in current memory? */

	u32 start;  /* Start wrt 0 */

	u32 end;    /* End wrt 0 */

};



struct cudbg_mem_desc {

	u32 base;

	u32 limit;

	u32 idx;

};



struct cudbg_meminfo {

	struct cudbg_mem_desc avail[4];

	struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];

	u32 avail_c;

	u32 mem_c;

	u32 up_ram_lo;

	u32 up_ram_hi;

	u32 up_extmem2_lo;

	u32 up_extmem2_hi;

	u32 rx_pages_data[3];

	u32 tx_pages_data[4];

	u32 p_structs;

	u32 reserved[12];

	u32 port_used[4];

	u32 port_alloc[4];

	u32 loopback_used[NCHAN];

	u32 loopback_alloc[NCHAN];

};



struct cudbg_cim_pif_la {

	int size;

	u8 data[0];
@@ -145,6 +185,7 @@ struct cudbg_tid_info_region_rev1 { 
	u32 reserved[16];

};



#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256

#define CUDBG_MAX_FL_QIDS 1024



struct cudbg_ch_cntxt {
@@ -334,6 +375,25 @@ static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = { 
	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */

};



#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61



static const u32 t5_pcie_config_array[][2] = {

	{0x0, 0x34},

	{0x3c, 0x40},

	{0x50, 0x64},

	{0x70, 0x80},

	{0x94, 0xa0},

	{0xb0, 0xb8},

	{0xd0, 0xd4},

	{0x100, 0x128},

	{0x140, 0x148},

	{0x150, 0x164},

	{0x170, 0x178},

	{0x180, 0x194},

	{0x1a0, 0x1b8},

	{0x1c0, 0x208},

};



static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {

	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */

	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

+5 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ enum cudbg_dbg_entity_type { 
	CUDBG_CIM_OBQ_NCSI = 17,

	CUDBG_EDC0 = 18,

	CUDBG_EDC1 = 19,

	CUDBG_MC0 = 20,

	CUDBG_MC1 = 21,

	CUDBG_RSS = 22,

	CUDBG_RSS_VF_CONF = 25,

	CUDBG_PATH_MTU = 27,
@@ -56,6 +58,7 @@ enum cudbg_dbg_entity_type { 
	CUDBG_SGE_INDIRECT = 37,

	CUDBG_ULPRX_LA = 41,

	CUDBG_TP_LA = 43,

	CUDBG_MEMINFO = 44,

	CUDBG_CIM_PIF_LA = 45,

	CUDBG_CLK = 46,

	CUDBG_CIM_OBQ_RXQ0 = 47,
@@ -63,6 +66,7 @@ enum cudbg_dbg_entity_type { 
	CUDBG_PCIE_INDIRECT = 50,

	CUDBG_PM_INDIRECT = 51,

	CUDBG_TID_INFO = 54,

	CUDBG_PCIE_CONFIG = 55,

	CUDBG_DUMP_CONTEXT = 56,

	CUDBG_MPS_TCAM = 57,

	CUDBG_VPD_DATA = 58,
@@ -74,6 +78,7 @@ enum cudbg_dbg_entity_type { 
	CUDBG_PBT_TABLE = 65,

	CUDBG_MBOX_LOG = 66,

	CUDBG_HMA_INDIRECT = 67,

	CUDBG_HMA = 68,

	CUDBG_MAX_ENTITY = 70,

};