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Commit 2dd057a4 authored by Ram Prakash Gupta's avatar Ram Prakash Gupta
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ARM: dts: msm: Add support for 2 lane ufs for khaje 

Add support for 2 lane and platform changes for UFS on
khaje platform.

Change-Id: Ibd48b494a93ead3fd6272bab8a0179c725445d8f
parent 017cfa7e

qcom/khaje-idp.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -176,12 +176,12 @@ 
};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v3-660";

	compatible = "qcom,ufs-phy-qmp-v4";



	vdda-phy-supply = <&L4A>; /* 0.9v */

	vdda-pll-supply = <&L12A>; /* 1.8v */

	vdda-phy-max-microamp = <51400>;

	vdda-pll-max-microamp = <14200>;

	vdda-pll-supply = <&L18A>; /* 1.8v */

	vdda-phy-max-microamp = <85700>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};
@@ -192,8 +192,8 @@ 
	vcc-supply = <&L24A>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&L11A>;

	vcc-max-microamp = <600000>;

	vccq2-max-microamp = <600000>;

	vcc-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;

	vccq2-pwr-collapse-sup;



	qcom,vddp-ref-clk-supply = <&L18A>;

qcom/khaje-qrd.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -178,12 +178,12 @@ 
};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qmp-v3-660";

	compatible = "qcom,ufs-phy-qmp-v4";



	vdda-phy-supply = <&L4A>; /* 0.9v */

	vdda-pll-supply = <&L12A>; /* 1.8v */

	vdda-phy-max-microamp = <51400>;

	vdda-pll-max-microamp = <14200>;

	vdda-pll-supply = <&L18A>; /* 1.8v */

	vdda-phy-max-microamp = <85700>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};
@@ -194,8 +194,8 @@ 
	vcc-supply = <&L24A>;

	vcc-voltage-level = <2950000 2960000>;

	vccq2-supply = <&L11A>;

	vcc-max-microamp = <600000>;

	vccq2-max-microamp = <600000>;

	vcc-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;

	vccq2-pwr-collapse-sup;



	qcom,vddp-ref-clk-supply = <&L18A>;

qcom/khaje.dtsi

+27 −5
Original line number Diff line number Diff line
@@ -1494,11 +1494,11 @@ 
	};



	ufsphy_mem: ufsphy_mem@4807000 {

		reg = <0x4807000 0xdb8>; /* PHY regs */

		reg = <0x4807000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <1>;

		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",
@@ -1518,7 +1518,7 @@ 
		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";



		lanes-per-direction = <1>;

		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		spm-level = <5>;
@@ -1530,7 +1530,8 @@ 
			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk";

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&gcc GCC_UFS_PHY_AXI_CLK>,

			<&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
@@ -1539,7 +1540,8 @@ 
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&rpmcc RPM_SMD_XO_CLK_SRC>,

			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<50000000 200000000>,

			<0 0>,
@@ -1548,6 +1550,7 @@ 
			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";
@@ -1569,18 +1572,37 @@ 
		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */

		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",

		"MAX";



		/* PM QoS */