Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Etnaviv DRM master device

=========================

The Etnaviv DRM master device is a virtual device needed to list all

Vivante GPU cores that comprise the GPU subsystem.

Required properties:

- compatible: Should be one of

    "fsl,imx-gpu-subsystem"

    "marvell,dove-gpu-subsystem"

- cores: Should contain a list of phandles pointing to Vivante GPU devices

example:

gpu-subsystem {

	compatible = "fsl,imx-gpu-subsystem";

	cores = <&gpu_2d>, <&gpu_3d>;

};

Vivante GPU core devices

========================

Required properties:

- compatible: Should be "vivante,gc"

  A more specific compatible is not needed, as the cores contain chip

  identification registers at fixed locations, which provide all the

  necessary information to the driver.

- reg: should be register base and length as documented in the

  datasheet

- interrupts: Should contain the cores interrupt line

- clocks: should contain one clock for entry in clock-names

  see Documentation/devicetree/bindings/clock/clock-bindings.txt

- clock-names:

   - "bus":    AXI/register clock

   - "core":   GPU core clock

   - "shader": Shader clock (only required if GPU has feature PIPE_3D)

Optional properties:

- power-domains: a power domain consumer specifier according to

  Documentation/devicetree/bindings/power/power_domain.txt

example:

gpu_3d: gpu@00130000 {

	compatible = "vivante,gc";

	reg = <0x00130000 0x4000>;

	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,

	         <&clks IMX6QDL_CLK_GPU3D_CORE>,

	         <&clks IMX6QDL_CLK_GPU3D_SHADER>;

	clock-names = "bus", "core", "shader";

	power-domains = <&gpc 1>;

};

Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)

DisplayPort is industry standard to accommodate the growing board adoption

of digital display technology within the PC and CE industries.

It consolidates the internal and external connection methods to reduce device

complexity and cost. It also supports necessary features for important cross

industry applications and provides performance scalability to enable the next

generation of displays that feature higher color depths, refresh rates, and

display resolutions.

eDP (embedded display port) device is compliant with Embedded DisplayPort

standard as follows,

- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.

- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.

eDP resides between FIMD and panel or FIMD and bridge such as LVDS.

The Exynos display port interface should be configured based on

The Exynos display port interface should be configured based on

the type of panel connected to it.

the type of panel connected to it.

		Hotplug detect GPIO.

		Hotplug detect GPIO.

			Indicates which GPIO should be used for hotplug

			Indicates which GPIO should be used for hotplug

			detection

			detection

	-video interfaces: Device node can contain video interface port

Video interfaces:

			    nodes according to [1].

  Device node can contain video interface port nodes according to [1].

  The following are properties specific to those nodes:

  endpoint node connected to bridge or panel node:

   - remote-endpoint: specifies the endpoint in panel or bridge node.

		      This node is required in all kinds of exynos dp

		      to represent the connection between dp and bridge

		      or dp and panel.

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

[1]: Documentation/devicetree/bindings/media/video-interfaces.txt

		};

		};

		ports {

		ports {

			port@0 {

			port {

				dp_out: endpoint {

				dp_out: endpoint {

					remote-endpoint = <&bridge_in>;

					remote-endpoint = <&dp_in>;

				};

			};

		};

		panel {

			...

			port {

				dp_in: endpoint {

					remote-endpoint = <&dp_out>;

				};

				};

			};

			};

		};

		};

- clocks: device clocks

- clocks: device clocks

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

- clock-names: the following clocks are required:

  * "mdp_core_clk"

  * "iface_clk"

  * "bus_clk"

  * "bus_clk"

  * "byte_clk"

  * "core_clk"

  * "core_mmss_clk"

  * "core_mmss_clk"

  * "iface_clk"

  * "byte_clk"

  * "mdp_core_clk"

  * "pixel_clk"

  * "pixel_clk"

  * "core_clk"

  For DSIv2, we need an additional clock:

   * "src_clk"

- vdd-supply: phandle to vdd regulator device node

- vdd-supply: phandle to vdd regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vddio-supply: phandle to vdd-io regulator device node

- vdda-supply: phandle to vdda regulator device node

- vdda-supply: phandle to vdda regulator device node

- qcom,dsi-phy: phandle to DSI PHY device node

- qcom,dsi-phy: phandle to DSI PHY device node

- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)

Optional properties:

Optional properties:

- panel@0: Node of panel connected to this DSI controller.

- panel@0: Node of panel connected to this DSI controller.

  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-hpm"

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

  regulator

- reg-names: The names of register regions. The following regions are required:

- reg-names: The names of register regions. The following regions are required:

Required properties:

Required properties:

- compatible:

- compatible:

  * "qcom,mdp" - mdp4

  * "qcom,mdp4" - mdp4

  * "qcom,mdp5" - mdp5

- reg: Physical base address and length of the controller's registers.

- reg: Physical base address and length of the controller's registers.

- interrupts: The interrupt signal from the display controller.

- interrupts: The interrupt signal from the display controller.

- connectors: array of phandles for output device(s)

- connectors: array of phandles for output device(s)

- clocks: device clocks

- clocks: device clocks

  See ../clocks/clock-bindings.txt for details.

  See ../clocks/clock-bindings.txt for details.

- clock-names: the following clocks are required:

- clock-names: the following clocks are required.

  For MDP4:

   * "core_clk"

   * "core_clk"

   * "iface_clk"

   * "iface_clk"

   * "lut_clk"

   * "src_clk"

   * "src_clk"

   * "hdmi_clk"

   * "hdmi_clk"

  * "mpd_clk"

   * "mdp_clk"

  For MDP5:

   * "bus_clk"

   * "iface_clk"

   * "core_clk_src"

   * "core_clk"

   * "lut_clk" (some MDP5 versions may not need this)

   * "vsync_clk"

Optional properties:

Optional properties:

- gpus: phandle for gpu device

- gpus: phandle for gpu device

	...

	...

	mdp: qcom,mdp@5100000 {

	mdp: qcom,mdp@5100000 {

		compatible = "qcom,mdp";

		compatible = "qcom,mdp4";

		reg = <0x05100000 0xf0000>;

		reg = <0x05100000 0xf0000>;

		interrupts = <GIC_SPI 75 0>;

		interrupts = <GIC_SPI 75 0>;

		connectors = <&hdmi>;

		connectors = <&hdmi>;