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Commit 2da454b4 authored by Chetan C R's avatar Chetan C R
Browse files

clk: qcom: cpu-sdm: Add cpu clock driver for SDM439 



Add support for CPU clock driver for scaling of cpu
clocks on SDM429 and SDM439 targets.

Change-Id: I57f09b487364ed9a3b9e93edaba7bae608e58ab9
Signed-off-by: default avatarChetan C R <cchinnad@codeaurora.org>
parent 00f69a7f

drivers/clk/qcom/clk-cpu-sdm.c

+399 −67
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 
	container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)



static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2, vdd_hf_levels);

static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_HF_PLL_NUM, 2, vdd_hf_levels);

static DEFINE_VDD_REGS_INIT(vdd_cpu_c0, 1);

static DEFINE_VDD_REGS_INIT(vdd_cpu_c1, 1);

static DEFINE_VDD_REGS_INIT(vdd_cpu_cci, 1);
@@ -55,10 +57,16 @@ static const struct parent_map apcs_mux_clk_parent_map0[] = { 
	{ P_APCS_CPU_PLL, 5 },

};



static const char *const apcs_mux_clk_parent_name0[] = {

static const char *const apcs_mux_clk_c1_parent_name0[] = {

	"bi_tcxo_ao",

	"gpll0_ao_out_main",

	"apcs_cpu_pll",

	"apcs_cpu_pll1",

};



static const char *const apcs_mux_clk_c0_parent_name0[] = {

	"bi_tcxo_ao",

	"gpll0_ao_out_main",

	"apcs_cpu_pll0",

};



static const struct parent_map apcs_mux_clk_parent_map1[] = {
@@ -246,13 +254,13 @@ static void spm_event(struct pll_spm_ctrl *apcs_pll_spm, bool enable) 
		writel_relaxed(val, (base + offset));

		/* Ensure that the write above goes through. */

		mb();



		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + force_event_offset);

		val |= BIT(bit);

		writel_relaxed(val, (base + offset + force_event_offset));

		/* Ensure that the write above goes through. */

		mb();



	} else {

		/* L2_SPM_FORCE_EVENT */

		val = readl_relaxed(base + offset + force_event_offset);
@@ -324,7 +332,49 @@ static const struct pll_config apcs_cpu_pll_config = { 
	.aux_output_mask = BIT(1),

};



static struct clk_pll apcs_cpu_pll = {

static struct clk_pll apcs_cpu_pll0 = {

	.mode_reg = 0x0,

	.l_reg = 0x4,

	.m_reg = 0x8,

	.n_reg = 0xc,

	.config_reg = 0x10,

	.status_reg = 0x1c,

	.status_bit = 16,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "apcs_cpu_pll0",

		.parent_names = (const char *[]){ "bi_tcxo_ao" },

		.num_parents = 1,

		.ops = &clk_pll_hf_ops,

		.vdd_class = &vdd_sr2_pll,

		.rate_max = (unsigned long[VDD_HF_PLL_NUM]) {

			[VDD_HF_PLL_SVS] = 1000000000,

			[VDD_HF_PLL_NOM] = 1900000000,

		},

		.num_rate_max = VDD_HF_PLL_NUM,

	},

};



static struct clk_regmap_mux_div apcs_mux_c0_clk = {

	.reg_offset = 0x0,

	.hid_width  = 5,

	.hid_shift  = 0,

	.src_width  = 3,

	.src_shift  = 8,

	.safe_src = 4,

	.safe_div = 1,

	.parent_map = apcs_mux_clk_parent_map0,

	.clk_nb.notifier_call = cpucc_notifier_cb,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "apcs_mux_c0_clk",

		.parent_names = apcs_mux_clk_c0_parent_name0,

		.num_parents = 3,

		.vdd_class = &vdd_cpu_c0,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &cpucc_clk_ops,

	},

};



static struct clk_pll apcs_cpu_pll1 = {

	.mode_reg = 0x0,

	.l_reg = 0x4,

	.m_reg = 0x8,
@@ -333,7 +383,7 @@ static struct clk_pll apcs_cpu_pll = { 
	.status_reg = 0x1c,

	.status_bit = 16,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "apcs_cpu_pll",

		.name = "apcs_cpu_pll1",

		.parent_names = (const char *[]){ "bi_tcxo_ao" },

		.num_parents = 1,

		.ops = &clk_pll_hf_ops,
@@ -358,7 +408,7 @@ static struct clk_regmap_mux_div apcs_mux_c1_clk = { 
	.clk_nb.notifier_call = cpucc_notifier_cb,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "apcs_mux_c1_clk",

		.parent_names = apcs_mux_clk_parent_name0,

		.parent_names = apcs_mux_clk_c1_parent_name0,

		.num_parents = 3,

		.vdd_class = &vdd_cpu_c1,

		.flags = CLK_SET_RATE_PARENT,
@@ -386,6 +436,7 @@ static struct clk_regmap_mux_div apcs_mux_cci_clk = { 
};



static const struct of_device_id match_table[] = {

	{ .compatible = "qcom,cpu-clock-sdm439" },

	{ .compatible = "qcom,cpu-clock-sdm429" },

	{ .compatible = "qcom,cpu-clock-qm215" },

	{}
@@ -400,15 +451,24 @@ static struct regmap_config cpu_regmap_config = { 
};



static struct clk_hw *cpu_clks_hws_qm215[] = {

	[APCS_CPU_PLL] = &apcs_cpu_pll.clkr.hw,

	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,

	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,

};



static struct clk_hw *cpu_clks_hws_sdm429[] = {

	[APCS_CPU_PLL] = &apcs_cpu_pll.clkr.hw,

	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,

	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,

	[APCS_MUX_CCI_CLK] = &apcs_mux_cci_clk.clkr.hw,

};



static struct clk_hw *cpu_clks_hws_sdm439[] = {

	[APCS_CPU_PLL1] = &apcs_cpu_pll1.clkr.hw,

	[APCS_MUX_C1_CLK] = &apcs_mux_c1_clk.clkr.hw,

	[APCS_MUX_CCI_CLK] = &apcs_mux_cci_clk.clkr.hw,

	[APCS_CPU_PLL0] = &apcs_cpu_pll0.clkr.hw,

	[APCS_MUX_C0_CLK] = &apcs_mux_c0_clk.clkr.hw,

};



static void cpucc_clk_get_speed_bin(struct platform_device *pdev, int *bin,

							int *version)

{
@@ -559,41 +619,74 @@ cpucc_clk_add_opp(struct clk_hw *hw, struct device *dev, unsigned long max_rate) 
	return 0;

}



static void cpucc_clk_print_opp_table(int cpu)

static void cpucc_clk_print_opp_table(int c0, int c1, bool is_sdm439)

{

	struct dev_pm_opp *oppfmax, *oppfmin;

	unsigned long apc_c1_fmax, apc_c1_fmin;

	u32 max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;

	unsigned long apc_c0_fmax, apc_c0_fmin, apc_c1_fmax, apc_c1_fmin;

	u32 max_index;



	max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;

	apc_c1_fmax = apcs_mux_c1_clk.clkr.hw.init->rate_max[max_index - 1];

	apc_c1_fmin = apcs_mux_c1_clk.clkr.hw.init->rate_max[1];



	oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(cpu),

	oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(c1),

		apc_c1_fmax, true);

	oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(cpu),

	oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(c1),

		apc_c1_fmin, true);

	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", cpu,



	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c1,

		 apc_c1_fmin, dev_pm_opp_get_voltage(oppfmin));

	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", cpu,

	pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c1,

		 apc_c1_fmax, dev_pm_opp_get_voltage(oppfmax));



	if (is_sdm439) {

		max_index = apcs_mux_c0_clk.clkr.hw.init->num_rate_max;

		apc_c0_fmax =

			apcs_mux_c0_clk.clkr.hw.init->rate_max[max_index - 1];

		apc_c0_fmin = apcs_mux_c0_clk.clkr.hw.init->rate_max[1];



		oppfmax = dev_pm_opp_find_freq_exact(get_cpu_device(c0),

			apc_c0_fmax, true);

		oppfmin = dev_pm_opp_find_freq_exact(get_cpu_device(c0),

			apc_c0_fmin, true);



		pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c0,

			 apc_c0_fmin, dev_pm_opp_get_voltage(oppfmin));

		pr_info("Clock_cpu:(cpu %d) OPP voltage for %lu: %ld\n", c0,

			 apc_c0_fmax, dev_pm_opp_get_voltage(oppfmax));

	}

}



static void cpucc_clk_populate_opp_table(struct platform_device *pdev)

static void cpucc_clk_populate_opp_table(struct platform_device *pdev,

		bool is_sdm439)

{

	unsigned long apc_c1_fmax;

	u32 max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;

	int cpu, sdm_cpu = 0;

	unsigned long apc_c1_fmax, apc_c0_fmax;

	u32 max_index;

	int cpu, sdm_cpu0 = 0, sdm_cpu1 = 0;



	if (is_sdm439) {

		max_index = apcs_mux_c0_clk.clkr.hw.init->num_rate_max;

		apc_c0_fmax =

			apcs_mux_c0_clk.clkr.hw.init->rate_max[max_index - 1];

	}



	max_index = apcs_mux_c1_clk.clkr.hw.init->num_rate_max;

	apc_c1_fmax = apcs_mux_c1_clk.clkr.hw.init->rate_max[max_index - 1];



	for_each_possible_cpu(cpu) {

		sdm_cpu = cpu;

		if (cpu/4 == 0) {

			sdm_cpu1 = cpu;

			WARN(cpucc_clk_add_opp(&apcs_mux_c1_clk.clkr.hw,

			get_cpu_device(cpu), apc_c1_fmax),

			"Failed to add OPP levels for apcs_mux_c1_clk\n");

		} else if (cpu/4 == 1 && is_sdm439) {

			sdm_cpu0 = cpu;

			WARN(cpucc_clk_add_opp(&apcs_mux_c0_clk.clkr.hw,

			get_cpu_device(cpu), apc_c0_fmax),

			"Failed to add OPP levels for apcs_mux_c0_clk\n");

		}

	cpucc_clk_print_opp_table(sdm_cpu);

	}

	cpucc_clk_print_opp_table(sdm_cpu0, sdm_cpu1, is_sdm439);

}



static int clock_sdm429_pm_event(struct notifier_block *this,
@@ -620,6 +713,32 @@ static struct notifier_block clock_sdm429_pm_notifier = { 
	.notifier_call = clock_sdm429_pm_event,

};



static int clock_sdm439_pm_event(struct notifier_block *this,

				unsigned long event, void *ptr)

{

	switch (event) {

	case PM_POST_HIBERNATION:

	case PM_POST_SUSPEND:

		clk_unprepare(apcs_mux_c0_clk.clkr.hw.clk);

		clk_unprepare(apcs_mux_c1_clk.clkr.hw.clk);

		clk_unprepare(apcs_mux_cci_clk.clkr.hw.clk);

		break;

	case PM_HIBERNATION_PREPARE:

	case PM_SUSPEND_PREPARE:

		clk_prepare(apcs_mux_c0_clk.clkr.hw.clk);

		clk_prepare(apcs_mux_c1_clk.clkr.hw.clk);

		clk_prepare(apcs_mux_cci_clk.clkr.hw.clk);

		break;

	default:

		break;

	}

	return NOTIFY_DONE;

}



static struct notifier_block clock_sdm439_pm_notifier = {

	.notifier_call = clock_sdm439_pm_event,

};



static int clock_qm215_pm_event(struct notifier_block *this,

				unsigned long event, void *ptr)

{
@@ -642,6 +761,126 @@ static struct notifier_block clock_qm215_pm_notifier = { 
	.notifier_call = clock_qm215_pm_event,

};



static int fixup_for_sdm439(struct platform_device *pdev, int speed_bin,

		int version)

{

	struct resource *res;

	void __iomem *base;

	struct device *dev = &pdev->dev;

	char prop_name[] = "qcom,speedX-bin-vX-XXX";

	int ret;



	 /* Rail Regulator for apcs_pll0 */

	vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,

			"vdd_sr2_pll");

	if (IS_ERR(vdd_sr2_pll.regulator[0])) {

		if (!(PTR_ERR(vdd_sr2_pll.regulator[0]) ==

			-EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get sr2_pll regulator\n");

		return PTR_ERR(vdd_sr2_pll.regulator[0]);

	}



	vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,

			"vdd_sr2_dig_ao");

	if (IS_ERR(vdd_sr2_pll.regulator[1])) {

		if (!(PTR_ERR(vdd_sr2_pll.regulator[1]) ==

			-EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get dig_ao regulator\n");

		return PTR_ERR(vdd_sr2_pll.regulator[1]);

	}



	/* Rail Regulator for APCS C0 mux */

	vdd_cpu_c0.regulator[0] = devm_regulator_get(&pdev->dev,

			"cpu-vdd");

	if (IS_ERR(vdd_cpu_c0.regulator[0])) {

		if (!(PTR_ERR(vdd_cpu_c0.regulator[0]) ==

					-EPROBE_DEFER))

			dev_err(&pdev->dev, "Unable to get C0 cpu-vdd regulator\n");

		return PTR_ERR(vdd_cpu_c0.regulator[0]);

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

			"apcs_pll0");

	if (res == NULL) {

		dev_err(&pdev->dev, "Failed to get apcs_pll0 resources\n");

		return -EINVAL;

	}



	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed map apcs_cpu_pll0 register base\n");

		return PTR_ERR(base);

	}



	cpu_regmap_config.name = "apcs_pll0";

	apcs_cpu_pll0.clkr.regmap = devm_regmap_init_mmio(dev, base,

						&cpu_regmap_config);

	if (IS_ERR(apcs_cpu_pll0.clkr.regmap)) {

		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll0\n");

		return PTR_ERR(apcs_cpu_pll0.clkr.regmap);

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

		 "apcs-c0-rcg-base");

	if (res == NULL) {

		dev_err(&pdev->dev, "Failed to get apcs-c0 resources\n");

		return -EINVAL;

	}



	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed map apcs-c0-rcg register base\n");

		return PTR_ERR(base);

	}



	cpu_regmap_config.name = "apcs-c0-rcg-base";

	apcs_mux_c0_clk.clkr.regmap = devm_regmap_init_mmio(dev, base,

						&cpu_regmap_config);

	if (IS_ERR(apcs_mux_c0_clk.clkr.regmap)) {

		dev_err(&pdev->dev, "Couldn't get regmap for apcs-c0-rcg\n");

		return PTR_ERR(apcs_mux_c0_clk.clkr.regmap);

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

		"spm_c0_base");

	if (res == NULL) {

		dev_err(&pdev->dev, "Failed to get spm-c0 resources\n");

		return -EINVAL;

	}



	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");

		return -ENOMEM;

	}

	apcs_cpu_pll0.spm_ctrl.spm_base = base;



	snprintf(prop_name, ARRAY_SIZE(prop_name),

		"qcom,speed%d-bin-v%d-%s", speed_bin, version, "c0");



	ret = cpucc_clk_get_fmax_vdd_class(pdev,

		(struct clk_init_data *)apcs_mux_c0_clk.clkr.hw.init,

			 prop_name);

	if (ret) {

		dev_err(&pdev->dev, "Didn't get c0 speed bin\n");



		snprintf(prop_name, ARRAY_SIZE(prop_name),

				"qcom,speed0-bin-v0-%s", "c0");

		ret = cpucc_clk_get_fmax_vdd_class(pdev,

			(struct clk_init_data *)

			apcs_mux_c0_clk.clkr.hw.init,

				prop_name);

		if (ret) {

			dev_err(&pdev->dev,

				"Unable to load safe voltage plan for c0\n");

			return ret;

		}

	}

	return 0;

}



static int cpucc_driver_probe(struct platform_device *pdev)

{

	struct resource *res;
@@ -651,7 +890,10 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	int i, ret, speed_bin, version, cpu;

	char prop_name[] = "qcom,speedX-bin-vX-XXX";

	void __iomem *base;

	bool is_sdm429, is_qm215;

	bool is_sdm439, is_sdm429, is_qm215;



	is_sdm439 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,cpu-clock-sdm439");



	is_sdm429 = of_device_is_compatible(pdev->dev.of_node,

						"qcom,cpu-clock-sdm429");
@@ -702,7 +944,7 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	}



	/* Rail Regulator for APCS CCI mux */

	if (is_sdm429) {

	if (is_sdm429 || is_sdm439) {

		vdd_cpu_cci.regulator[0] =

			devm_regulator_get(&pdev->dev, "cpu-vdd");

		if (IS_ERR(vdd_cpu_cci.regulator[0])) {
@@ -714,26 +956,40 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
		}

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_pll");

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs_pll1");

	if (res == NULL) {

		dev_err(&pdev->dev, "Failed to get apcs_pll resources\n");

		dev_err(&pdev->dev, "Failed to get apcs_pll1 resources\n");

		return -EINVAL;

	}



	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed map apcs_cpu_pll register base\n");

		dev_err(&pdev->dev, "Failed map apcs_cpu_pll1 register base\n");

		return PTR_ERR(base);

	}



	cpu_regmap_config.name = "apcs_pll";

	apcs_cpu_pll.clkr.regmap = devm_regmap_init_mmio(dev, base,

	cpu_regmap_config.name = "apcs_pll1";

	apcs_cpu_pll1.clkr.regmap = devm_regmap_init_mmio(dev, base,

							&cpu_regmap_config);

	if (IS_ERR(apcs_cpu_pll.clkr.regmap)) {

		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll\n");

		return PTR_ERR(apcs_cpu_pll.clkr.regmap);

	if (IS_ERR(apcs_cpu_pll1.clkr.regmap)) {

		dev_err(&pdev->dev, "Couldn't get regmap for apcs_cpu_pll1\n");

		return PTR_ERR(apcs_cpu_pll1.clkr.regmap);

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

		"spm_c1_base");

	if (res == NULL) {

		dev_err(&pdev->dev, "Failed to get spm-c1 resources\n");

		return -EINVAL;

	}



	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base)) {

		dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");

		return -ENOMEM;

	}

	apcs_cpu_pll1.spm_ctrl.spm_base = base;



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

			 "apcs-c1-rcg-base");

	if (res == NULL) {
@@ -755,7 +1011,7 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
		return PTR_ERR(apcs_mux_c1_clk.clkr.regmap);

	}



	if (is_sdm429) {

	if (is_sdm429 || is_sdm439) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

				 "apcs-cci-rcg-base");

		if (res == NULL) {
@@ -776,21 +1032,6 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
			dev_err(&pdev->dev, "Couldn't get regmap for apcs-cci-rcg\n");

			return PTR_ERR(apcs_mux_cci_clk.clkr.regmap);

		}



		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

				"spm_c1_base");

		if (res == NULL) {

			dev_err(&pdev->dev, "Failed to get spm-c1 resources\n");

			return -EINVAL;

		}



		base = devm_ioremap_resource(dev, res);

		if (IS_ERR(base)) {

			dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");

			return -ENOMEM;

		}



		apcs_pll_spm.spm_base = base;

	}



	/* Get speed bin information */
@@ -804,17 +1045,21 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
				 prop_name);

	if (ret) {

		dev_err(&pdev->dev, "Didn't get c1 speed bin\n");



		snprintf(prop_name, ARRAY_SIZE(prop_name),

				"qcom,speed0-bin-v0-%s", "c1");

		ret = cpucc_clk_get_fmax_vdd_class(pdev,

				(struct clk_init_data *)

				apcs_mux_c1_clk.clkr.hw.init,

					prop_name);

		if (ret) {

			dev_err(&pdev->dev, "Unable to get vdd class for c1\n");

			dev_err(&pdev->dev,

				"Unable to load safe voltage plan for c1\n");

			return ret;

		}

	}



	if (is_sdm429) {

	if (is_sdm429 || is_sdm439) {

		snprintf(prop_name, ARRAY_SIZE(prop_name),

			"qcom,speed%d-bin-v%d-%s", speed_bin, version, "cci");
@@ -823,17 +1068,29 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
				 prop_name);

		if (ret) {

			dev_err(&pdev->dev, "Didn't get cci speed bin\n");



			snprintf(prop_name, ARRAY_SIZE(prop_name),

				"qcom,speed0-bin-v0-%s", "cci");

			ret = cpucc_clk_get_fmax_vdd_class(pdev,

				(struct clk_init_data *)

				apcs_mux_cci_clk.clkr.hw.init,

					prop_name);

			if (ret) {

				dev_err(&pdev->dev, "Unable get vdd class for cci\n");

				dev_err(&pdev->dev,

					"Unable to load safe voltage plan for cci\n");

				return ret;

			}

		}

	}



	if (is_sdm439) {

		ret = fixup_for_sdm439(pdev, speed_bin, version);

		if (ret) {

			dev_err(&pdev->dev, "Unable get sdm439 clocks\n");

			return ret;

		}

	}



	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);

	if (!data)

		return -ENOMEM;
@@ -864,6 +1121,19 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
			}

			data->hws[i] = cpu_clks_hws_qm215[i];

		}

	} else if (is_sdm439) {

		data->num = ARRAY_SIZE(cpu_clks_hws_sdm439);



		for (i = 0; i < ARRAY_SIZE(cpu_clks_hws_sdm439); i++) {

			ret = devm_clk_hw_register(dev,

					cpu_clks_hws_sdm439[i]);

			if (ret) {

				dev_err(&pdev->dev,

					"Failed to register clock\n");

				return ret;

			}

			data->hws[i] = cpu_clks_hws_sdm439[i];

		}

	}



	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, data);
@@ -873,6 +1143,16 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	}



	/* For safe freq switching during rate change */

	if (is_sdm439) {

		ret = clk_notifier_register(apcs_mux_c0_clk.clkr.hw.clk,

						&apcs_mux_c0_clk.clk_nb);

		if (ret) {

			dev_err(dev, "failed to register clock notifier: %d\n",

					ret);

			return ret;

		}

	}



	ret = clk_notifier_register(apcs_mux_c1_clk.clkr.hw.clk,

						&apcs_mux_c1_clk.clk_nb);

	if (ret) {
@@ -886,19 +1166,29 @@ static int cpucc_driver_probe(struct platform_device *pdev) 
	 */

	get_online_cpus();

	for_each_online_cpu(cpu) {

		if (!(cpu/4)) {

			WARN(clk_prepare_enable(apcs_mux_c1_clk.clkr.hw.clk),

				"Unable to turn on CPU clock\n");

		if (is_sdm429)

		}



		if (cpu/4 && is_sdm439) {

			WARN(clk_prepare_enable(apcs_mux_c0_clk.clkr.hw.clk),

				"Unable to turn on CPU clock\n");

		}



		if (is_sdm429 || is_sdm439)

			clk_prepare_enable(apcs_mux_cci_clk.clkr.hw.clk);

	}

	put_online_cpus();



	if (is_sdm429)

	if (is_sdm439)

		register_pm_notifier(&clock_sdm439_pm_notifier);

	else if (is_sdm429)

		register_pm_notifier(&clock_sdm429_pm_notifier);

	else if (is_qm215)

		register_pm_notifier(&clock_qm215_pm_notifier);



	cpucc_clk_populate_opp_table(pdev);

	cpucc_clk_populate_opp_table(pdev, is_sdm439);

	dev_info(dev, "CPU clock Driver probed successfully\n");



	return ret;
@@ -925,20 +1215,42 @@ static void __exit cpu_clk_exit(void) 
module_exit(cpu_clk_exit);



#define REG_OFFSET	0x4

#define APCS_PLL	0x0b016000

#define APCS_PLL0	0x0b116000

#define APCS_PLL1	0x0b016000

#define A53SS_MUX_C0	0x0b111050

#define A53SS_MUX_C1	0x0b011050



static void config_enable_sr2_pll(void __iomem *base)

{

	/* Configure L/M/N values */

	writel_relaxed(0x34, base + apcs_cpu_pll0.l_reg);

	writel_relaxed(0x0, base + apcs_cpu_pll0.m_reg);

	writel_relaxed(0x1, base + apcs_cpu_pll0.n_reg);



	/* Configure USER_CTL value */

	writel_relaxed(0xf, base + apcs_cpu_pll0.config_reg);



	/* Enable the pll */

	writel_relaxed(0x2, base + apcs_cpu_pll0.mode_reg);

	udelay(2);

	writel_relaxed(0x6, base + apcs_cpu_pll0.mode_reg);

	udelay(50);

	writel_relaxed(0x7, base + apcs_cpu_pll0.mode_reg);

	/* Ensure that the writes go through before enabling PLL */

	mb();

}



static void config_enable_hf_pll(void __iomem *base)

{

	/* Configure USER_CTL value */

	writel_relaxed(0xf, base + apcs_cpu_pll.config_reg);

	writel_relaxed(0xf, base + apcs_cpu_pll1.config_reg);



	/* Enable the pll */

	writel_relaxed(0x2, base + apcs_cpu_pll.mode_reg);

	writel_relaxed(0x2, base + apcs_cpu_pll1.mode_reg);

	udelay(2);

	writel_relaxed(0x6, base + apcs_cpu_pll.mode_reg);

	writel_relaxed(0x6, base + apcs_cpu_pll1.mode_reg);

	udelay(50);

	writel_relaxed(0x7, base + apcs_cpu_pll.mode_reg);

	writel_relaxed(0x7, base + apcs_cpu_pll1.mode_reg);

	/* Ensure that the writes go through before enabling PLL */

	mb();

}
@@ -948,9 +1260,16 @@ static int __init cpu_clock_init(void) 
	struct device_node *dev;

	void __iomem  *base;

	int count, regval = 0;

	bool is_sdm439 = false;

	unsigned long enable_mask = GENMASK(2, 0);

	dev = of_find_compatible_node(NULL, NULL, "qcom,cpu-clock-sdm439");



	dev = of_find_compatible_node(NULL, NULL, "qcom,cpu-clock-sdm429");

	if (dev)

		is_sdm439 = true;



	if (!dev)

		dev = of_find_compatible_node(NULL, NULL,

				"qcom,cpu-clock-sdm429");



	if (!dev)

		dev = of_find_compatible_node(NULL, NULL,
@@ -960,7 +1279,19 @@ static int __init cpu_clock_init(void) 
		return -ENOMEM;

	}



	base = ioremap_nocache(APCS_PLL, SZ_64);

	if (is_sdm439) {

		base = ioremap_nocache(APCS_PLL0, SZ_64);

		if (!base)

			return -ENOMEM;



		regval = readl_relaxed(base);

		if (!((regval & enable_mask) == enable_mask))

			config_enable_sr2_pll(base);



		iounmap(base);

	}



	base = ioremap_nocache(APCS_PLL1, SZ_64);

	if (!base)

		return -ENOMEM;
@@ -1000,6 +1331,7 @@ static int __init cpu_clock_init(void) 
		udelay(1);

	}



	iounmap(base);

	return 0;

}

early_initcall(cpu_clock_init);