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Commit 2d888f48 authored by Suzuki K. Poulose's avatar Suzuki K. Poulose Committed by Catalin Marinas
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arm64: Emulate SETEND for AArch32 tasks 



Emulate deprecated 'setend' instruction for AArch32 bit tasks.

	setend [le/be] - Sets the endianness of EL0

On systems with CPUs which support mixed endian at EL0, the hardware
support for the instruction can be enabled by setting the SCTLR_EL1.SED
bit. Like the other emulated instructions it is controlled by an entry in
/proc/sys/abi/. For more information see :
	Documentation/arm64/legacy_instructions.txt

The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which
will be reflected in the PSTATE.E in AArch32 context.

This patch also restores the native endianness for the execution of signal
handlers, since the process could have changed the endianness.

Note: All CPUs on the system must have mixed endian support at EL0. Once the
handler is registered, hotplugging a CPU which doesn't support mixed endian,
could lead to unexpected results/behavior in applications.

Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 736d474f

Documentation/arm64/legacy_instructions.txt

+12 −0
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ The default mode depends on the status of the instruction in the 
architecture. Deprecated instructions should default to emulation

while obsolete instructions must be undefined by default.



Note: Instruction emulation may not be possible in all cases. See

individual instruction notes for further information.



Supported legacy instructions

-----------------------------

* SWP{B}
@@ -43,3 +46,12 @@ Default: Undef (0) 
Node: /proc/sys/abi/cp15_barrier

Status: Deprecated

Default: Emulate (1)



* SETEND

Node: /proc/sys/abi/setend

Status: Deprecated

Default: Emulate (1)*

Note: All the cpus on the system must have mixed endian support at EL0

for this feature to be enabled. If a new CPU - which doesn't support mixed

endian - is hotplugged in after this feature has been enabled, there could

be unexpected results in the application.

arch/arm64/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -540,6 +540,21 @@ config CP15_BARRIER_EMULATION 


	  If unsure, say Y



config SETEND_EMULATION

	bool "Emulate SETEND instruction"

	help

	  The SETEND instruction alters the data-endianness of the

	  AArch32 EL0, and is deprecated in ARMv8.



	  Say Y here to enable software emulation of the instruction

	  for AArch32 userspace code.



	  Note: All the cpus on the system must have mixed endian support at EL0

	  for this feature to be enabled. If a new CPU - which doesn't support mixed

	  endian - is hotplugged in after this feature has been enabled, there could

	  be unexpected results in the applications.



	  If unsure, say Y

endif



endmenu

arch/arm64/include/asm/cputype.h

+1 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@ 
	(((mmfr0) & ID_AA64MMFR0_BIGEND_MASK) >> ID_AA64MMFR0_BIGEND_SHIFT)



#define SCTLR_EL1_CP15BEN	(0x1 << 5)

#define SCTLR_EL1_SED		(0x1 << 8)



#ifndef __ASSEMBLY__

arch/arm64/include/asm/ptrace.h

+7 −0
Original line number Diff line number Diff line
@@ -58,6 +58,13 @@ 
#define COMPAT_PSR_Z_BIT	0x40000000

#define COMPAT_PSR_N_BIT	0x80000000

#define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */



#ifdef CONFIG_CPU_BIG_ENDIAN

#define COMPAT_PSR_ENDSTATE	COMPAT_PSR_E_BIT

#else

#define COMPAT_PSR_ENDSTATE	0

#endif



/*

 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a

 * process is located in memory.

arch/arm64/kernel/armv8_deprecated.c

+80 −0
Original line number Diff line number Diff line
@@ -548,6 +548,79 @@ static struct insn_emulation_ops cp15_barrier_ops = { 
	.set_hw_mode = cp15_barrier_set_hw_mode,

};



static int setend_set_hw_mode(bool enable)

{

	if (!cpu_supports_mixed_endian_el0())

		return -EINVAL;



	if (enable)

		config_sctlr_el1(SCTLR_EL1_SED, 0);

	else

		config_sctlr_el1(0, SCTLR_EL1_SED);

	return 0;

}



static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)

{

	char *insn;



	perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);



	if (big_endian) {

		insn = "setend be";

		regs->pstate |= COMPAT_PSR_E_BIT;

	} else {

		insn = "setend le";

		regs->pstate &= ~COMPAT_PSR_E_BIT;

	}



	trace_instruction_emulation(insn, regs->pc);

	pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",

			current->comm, (unsigned long)current->pid, regs->pc);



	return 0;

}



static int a32_setend_handler(struct pt_regs *regs, u32 instr)

{

	int rc = compat_setend_handler(regs, (instr >> 9) & 1);

	regs->pc += 4;

	return rc;

}



static int t16_setend_handler(struct pt_regs *regs, u32 instr)

{

	int rc = compat_setend_handler(regs, (instr >> 3) & 1);

	regs->pc += 2;

	return rc;

}



static struct undef_hook setend_hooks[] = {

	{

		.instr_mask	= 0xfffffdff,

		.instr_val	= 0xf1010000,

		.pstate_mask	= COMPAT_PSR_MODE_MASK,

		.pstate_val	= COMPAT_PSR_MODE_USR,

		.fn		= a32_setend_handler,

	},

	{

		/* Thumb mode */

		.instr_mask	= 0x0000fff7,

		.instr_val	= 0x0000b650,

		.pstate_mask	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),

		.pstate_val	= (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),

		.fn		= t16_setend_handler,

	},

	{}

};



static struct insn_emulation_ops setend_ops = {

	.name = "setend",

	.status = INSN_DEPRECATED,

	.hooks = setend_hooks,

	.set_hw_mode = setend_set_hw_mode,

};



static int insn_cpu_hotplug_notify(struct notifier_block *b,

			      unsigned long action, void *hcpu)

{
@@ -573,6 +646,13 @@ static int __init armv8_deprecated_init(void) 
	if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))

		register_insn_emulation(&cp15_barrier_ops);



	if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {

		if(system_supports_mixed_endian_el0())

			register_insn_emulation(&setend_ops);

		else

			pr_info("setend instruction emulation is not supported on the system");

	}



	register_cpu_notifier(&insn_cpu_hotplug_notifier);

	register_insn_emulation_sysctl(ctl_abi);