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Commit 2d65d464 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "drm/msm/sde: add field for perf features in hw block info"

parents f263d84c 128edc12

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+18 −45
Original line number Diff line number Diff line
@@ -983,9 +983,9 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
			sspp->id - SSPP_VIG0);

	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;

	sspp->type = SSPP_TYPE_VIG;

	set_bit(SDE_SSPP_QOS, &sspp->features);

	set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);

	if (sde_cfg->vbif_qos_nlvl == 8)

		set_bit(SDE_SSPP_QOS_8LVL, &sspp->features);

		set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);

	(*vig_count)++;



	if (!prop_value)
@@ -1111,9 +1111,9 @@ static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg, 
			sspp->id - SSPP_VIG0);

	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;

	sspp->type = SSPP_TYPE_RGB;

	set_bit(SDE_SSPP_QOS, &sspp->features);

	set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);

	if (sde_cfg->vbif_qos_nlvl == 8)

		set_bit(SDE_SSPP_QOS_8LVL, &sspp->features);

		set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);

	(*rgb_count)++;



	if (!prop_value)
@@ -1189,9 +1189,9 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 
	snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",

			sspp->id - SSPP_VIG0);

	sspp->type = SSPP_TYPE_DMA;

	set_bit(SDE_SSPP_QOS, &sspp->features);

	set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);

	if (sde_cfg->vbif_qos_nlvl == 8)

		set_bit(SDE_SSPP_QOS_8LVL, &sspp->features);

		set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);

	(*dma_count)++;



	if (!prop_value)
@@ -1373,13 +1373,14 @@ static int sde_sspp_parse_dt(struct device_node *np, 
		set_bit(SDE_SSPP_SRC, &sspp->features);



		if (sde_cfg->has_cdp)

			set_bit(SDE_SSPP_CDP, &sspp->features);

			set_bit(SDE_PERF_SSPP_CDP, &sspp->perf_features);



		if (sde_cfg->ts_prefill_rev == 1) {

			set_bit(SDE_SSPP_TS_PREFILL, &sspp->features);

			set_bit(SDE_PERF_SSPP_TS_PREFILL, &sspp->perf_features);

		} else if (sde_cfg->ts_prefill_rev == 2) {

			set_bit(SDE_SSPP_TS_PREFILL, &sspp->features);

			set_bit(SDE_SSPP_TS_PREFILL_REC1, &sspp->features);

			set_bit(SDE_PERF_SSPP_TS_PREFILL, &sspp->perf_features);

			set_bit(SDE_PERF_SSPP_TS_PREFILL_REC1,

					&sspp->perf_features);

		}



		sblk->smart_dma_priority =
@@ -3339,21 +3340,12 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg, 
	}



	dma_list_size = ARRAY_SIZE(plane_formats);

	vig_list_size = ARRAY_SIZE(plane_formats_yuv);

	virt_vig_list_size = ARRAY_SIZE(plane_formats);

	wb2_list_size = ARRAY_SIZE(wb2_formats);



	dma_list_size += ARRAY_SIZE(rgb_10bit_formats);

	vig_list_size += ARRAY_SIZE(rgb_10bit_formats)

		+ ARRAY_SIZE(tp10_ubwc_formats)

		+ ARRAY_SIZE(p010_formats);

	virt_vig_list_size += ARRAY_SIZE(rgb_10bit_formats);



	vig_list_size = ARRAY_SIZE(plane_formats_vig);

	if (sde_cfg->has_vig_p010)

		vig_list_size += ARRAY_SIZE(p010_ubwc_formats);

	virt_vig_list_size = ARRAY_SIZE(plane_formats);

	wb2_list_size = ARRAY_SIZE(wb2_formats);



	wb2_list_size += ARRAY_SIZE(rgb_10bit_formats)

		+ ARRAY_SIZE(tp10_ubwc_formats);



	sde_cfg->dma_formats = kcalloc(dma_list_size,

		sizeof(struct sde_format_extended), GFP_KERNEL);
@@ -3386,39 +3378,20 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg, 


	index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,

		0, plane_formats, ARRAY_SIZE(plane_formats));

	index += sde_copy_formats(sde_cfg->dma_formats, dma_list_size,

		index, rgb_10bit_formats,

		ARRAY_SIZE(rgb_10bit_formats));



	index = sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

		0, plane_formats_yuv, ARRAY_SIZE(plane_formats_yuv));

	index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

		index, rgb_10bit_formats,

		ARRAY_SIZE(rgb_10bit_formats));

	index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

		index, p010_formats, ARRAY_SIZE(p010_formats));

		0, plane_formats_vig, ARRAY_SIZE(plane_formats_vig));

	if (sde_cfg->has_vig_p010)

		index += sde_copy_formats(sde_cfg->vig_formats,

			vig_list_size, index, p010_ubwc_formats,

			ARRAY_SIZE(p010_ubwc_formats));

	index += sde_copy_formats(sde_cfg->vig_formats, vig_list_size,

		index, tp10_ubwc_formats,

		ARRAY_SIZE(tp10_ubwc_formats));



	index = sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,

		0, plane_formats, ARRAY_SIZE(plane_formats));

	index += sde_copy_formats(sde_cfg->virt_vig_formats, virt_vig_list_size,

		index, rgb_10bit_formats,

		ARRAY_SIZE(rgb_10bit_formats));



	index = sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,

		0, wb2_formats, ARRAY_SIZE(wb2_formats));

	index += sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,

		index, rgb_10bit_formats,

		ARRAY_SIZE(rgb_10bit_formats));

	index += sde_copy_formats(sde_cfg->wb_formats, wb2_list_size,

		index, tp10_ubwc_formats,

		ARRAY_SIZE(tp10_ubwc_formats));



end:

	return rc;

}
@@ -3560,8 +3533,8 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, 
			sde_cfg->max_mixer_blendstages - SDE_STAGE_0;



		for (i = 0; i < sde_cfg->sspp_count; i++)

			set_bit(SDE_SSPP_QOS_FL_NOCALC,

					&sde_cfg->sspp[i].features);

			set_bit(SDE_PERF_SSPP_QOS_FL_NOCALC,

					&sde_cfg->sspp[i].perf_features);

	}



	for (i = 0; i < sde_cfg->sspp_count; i++) {

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+23 −13
Original line number Diff line number Diff line
@@ -157,15 +157,10 @@ enum { 
 * @SDE_SSPP_MEMCOLOR        Memory Color Support

 * @SDE_SSPP_PCC,            Color correction support

 * @SDE_SSPP_CURSOR,         SSPP can be used as a cursor layer

 * @SDE_SSPP_QOS,            SSPP support QoS control, danger/safe/creq

 * @SDE_SSPP_QOS_8LVL,       SSPP support 8-level QoS control

 * @SDE_SSPP_EXCL_RECT,      SSPP supports exclusion rect

 * @SDE_SSPP_SMART_DMA_V1,   SmartDMA 1.0 support

 * @SDE_SSPP_SMART_DMA_V2,   SmartDMA 2.0 support

 * @SDE_SSPP_SMART_DMA_V2p5, SmartDMA 2.5 support

 * @SDE_SSPP_TS_PREFILL      Supports prefill with traffic shaper

 * @SDE_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec

 * @SDE_SSPP_CDP             Supports client driven prefetch

 * @SDE_SSPP_VIG_IGC,        VIG 1D LUT IGC

 * @SDE_SSPP_VIG_GAMUT,      VIG 3D LUT Gamut

 * @SDE_SSPP_DMA_IGC,        DMA 1D LUT IGC
@@ -175,7 +170,6 @@ enum { 
 * @SDE_SSPP_DGM_CSC         Support of color space conversion in DGM block

 * @SDE_SSPP_SEC_UI_ALLOWED   Allows secure-ui layers

 * @SDE_SSPP_BLOCK_SEC_UI    Blocks secure-ui layers

 * @SDE_SSPP_QOS_FL_NOCALC   Avoid fill level calculation for QoS/danger/safe

 * @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support

 * @SDE_SSPP_MAX             maximum value

 */
@@ -190,15 +184,10 @@ enum { 
	SDE_SSPP_MEMCOLOR,

	SDE_SSPP_PCC,

	SDE_SSPP_CURSOR,

	SDE_SSPP_QOS,

	SDE_SSPP_QOS_8LVL,

	SDE_SSPP_EXCL_RECT,

	SDE_SSPP_SMART_DMA_V1,

	SDE_SSPP_SMART_DMA_V2,

	SDE_SSPP_SMART_DMA_V2p5,

	SDE_SSPP_TS_PREFILL,

	SDE_SSPP_TS_PREFILL_REC1,

	SDE_SSPP_CDP,

	SDE_SSPP_VIG_IGC,

	SDE_SSPP_VIG_GAMUT,

	SDE_SSPP_DMA_IGC,
@@ -208,11 +197,30 @@ enum { 
	SDE_SSPP_DGM_CSC,

	SDE_SSPP_SEC_UI_ALLOWED,

	SDE_SSPP_BLOCK_SEC_UI,

	SDE_SSPP_QOS_FL_NOCALC,

	SDE_SSPP_SCALER_QSEED3LITE,

	SDE_SSPP_MAX

};



/**

 * SDE performance features

 * @SDE_PERF_SSPP_QOS,            SSPP support QoS control, danger/safe/creq

 * @SDE_PERF_SSPP_QOS_8LVL,       SSPP support 8-level QoS control

 * @SDE_PERF_SSPP_TS_PREFILL      Supports prefill with traffic shaper

 * @SDE_PERF_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec

 * @SDE_PERF_SSPP_CDP             Supports client driven prefetch

 * @SDE_PERF_SSPP_QOS_FL_NOCALC   Avoid fill level calc for QoS/danger/safe

 * @SDE_PERF_SSPP_MAX             Maximum value

 */

enum {

	SDE_PERF_SSPP_QOS = 0x1,

	SDE_PERF_SSPP_QOS_8LVL,

	SDE_PERF_SSPP_TS_PREFILL,

	SDE_PERF_SSPP_TS_PREFILL_REC1,

	SDE_PERF_SSPP_CDP,

	SDE_PERF_SSPP_QOS_FL_NOCALC,

	SDE_PERF_SSPP_MAX

};



/*

 * MIXER sub-blocks/features

 * @SDE_MIXER_LAYER           Layer mixer layer blend configuration,
@@ -403,13 +411,15 @@ enum { 
 * @base:              register base offset to mdss

 * @len:               length of hardware block

 * @features           bit mask identifying sub-blocks/features

 * @perf_features   bit mask identifying performance sub-blocks/features

 */

#define SDE_HW_BLK_INFO \

	char name[SDE_HW_BLK_NAME_LEN]; \

	u32 id; \

	u32 base; \

	u32 len; \

	unsigned long features

	unsigned long features; \

	unsigned long perf_features



/**

 * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE

drivers/gpu/drm/msm/sde/sde_hw_catalog_format.h

+61 −85
Original line number Diff line number Diff line
@@ -5,73 +5,63 @@ 


#include "sde_hw_mdss.h"



#define RGB_10BIT_FMTS	{DRM_FORMAT_BGRA1010102, 0}, \

	{DRM_FORMAT_BGRX1010102, 0}, \

	{DRM_FORMAT_RGBA1010102, 0}, \

	{DRM_FORMAT_RGBX1010102, 0}, \

	{DRM_FORMAT_ABGR2101010, 0}, \

	{DRM_FORMAT_ABGR2101010, DRM_FORMAT_MOD_QCOM_COMPRESSED}, \

	{DRM_FORMAT_XBGR2101010, 0}, \

	{DRM_FORMAT_XBGR2101010, DRM_FORMAT_MOD_QCOM_COMPRESSED}, \

	{DRM_FORMAT_ARGB2101010, 0}, \

	{DRM_FORMAT_XRGB2101010, 0}



#define RGB_FMTS	{DRM_FORMAT_ARGB8888, 0}, \

	{DRM_FORMAT_ABGR8888, 0}, \

	{DRM_FORMAT_RGBA8888, 0}, \

	{DRM_FORMAT_ABGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED}, \

	{DRM_FORMAT_BGRA8888, 0}, \

	{DRM_FORMAT_XRGB8888, 0}, \

	{DRM_FORMAT_RGBX8888, 0}, \

	{DRM_FORMAT_BGRX8888, 0}, \

	{DRM_FORMAT_XBGR8888, 0}, \

	{DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED}, \

	{DRM_FORMAT_RGB888, 0}, \

	{DRM_FORMAT_BGR888, 0}, \

	{DRM_FORMAT_RGB565, 0}, \

	{DRM_FORMAT_BGR565, DRM_FORMAT_MOD_QCOM_COMPRESSED}, \

	{DRM_FORMAT_BGR565, 0}, \

	{DRM_FORMAT_ARGB1555, 0}, \

	{DRM_FORMAT_ABGR1555, 0}, \

	{DRM_FORMAT_RGBA5551, 0}, \

	{DRM_FORMAT_BGRA5551, 0}, \

	{DRM_FORMAT_XRGB1555, 0}, \

	{DRM_FORMAT_XBGR1555, 0}, \

	{DRM_FORMAT_RGBX5551, 0}, \

	{DRM_FORMAT_BGRX5551, 0}, \

	{DRM_FORMAT_ARGB4444, 0}, \

	{DRM_FORMAT_ABGR4444, 0}, \

	{DRM_FORMAT_RGBA4444, 0}, \

	{DRM_FORMAT_BGRA4444, 0}, \

	{DRM_FORMAT_XRGB4444, 0}, \

	{DRM_FORMAT_XBGR4444, 0}, \

	{DRM_FORMAT_RGBX4444, 0}, \

	{DRM_FORMAT_BGRX4444, 0}



#define TP10_UBWC_FMTS	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED | \

		DRM_FORMAT_MOD_QCOM_DX | DRM_FORMAT_MOD_QCOM_TIGHT}



#define P010_FMTS	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX}





static const struct sde_format_extended plane_formats[] = {

	{DRM_FORMAT_ARGB8888, 0},

	{DRM_FORMAT_ABGR8888, 0},

	{DRM_FORMAT_RGBA8888, 0},

	{DRM_FORMAT_ABGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_BGRA8888, 0},

	{DRM_FORMAT_XRGB8888, 0},

	{DRM_FORMAT_RGBX8888, 0},

	{DRM_FORMAT_BGRX8888, 0},

	{DRM_FORMAT_XBGR8888, 0},

	{DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_RGB888, 0},

	{DRM_FORMAT_BGR888, 0},

	{DRM_FORMAT_RGB565, 0},

	{DRM_FORMAT_BGR565, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_BGR565, 0},

	{DRM_FORMAT_ARGB1555, 0},

	{DRM_FORMAT_ABGR1555, 0},

	{DRM_FORMAT_RGBA5551, 0},

	{DRM_FORMAT_BGRA5551, 0},

	{DRM_FORMAT_XRGB1555, 0},

	{DRM_FORMAT_XBGR1555, 0},

	{DRM_FORMAT_RGBX5551, 0},

	{DRM_FORMAT_BGRX5551, 0},

	{DRM_FORMAT_ARGB4444, 0},

	{DRM_FORMAT_ABGR4444, 0},

	{DRM_FORMAT_RGBA4444, 0},

	{DRM_FORMAT_BGRA4444, 0},

	{DRM_FORMAT_XRGB4444, 0},

	{DRM_FORMAT_XBGR4444, 0},

	{DRM_FORMAT_RGBX4444, 0},

	{DRM_FORMAT_BGRX4444, 0},

	RGB_FMTS,

	RGB_10BIT_FMTS,

	{0, 0},

};



static const struct sde_format_extended plane_formats_yuv[] = {

	{DRM_FORMAT_ARGB8888, 0},

	{DRM_FORMAT_ABGR8888, 0},

	{DRM_FORMAT_RGBA8888, 0},

	{DRM_FORMAT_BGRX8888, 0},

	{DRM_FORMAT_ABGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_BGRA8888, 0},

	{DRM_FORMAT_XRGB8888, 0},

	{DRM_FORMAT_XBGR8888, 0},

	{DRM_FORMAT_RGBX8888, 0},

	{DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_RGB888, 0},

	{DRM_FORMAT_BGR888, 0},

	{DRM_FORMAT_RGB565, 0},

	{DRM_FORMAT_BGR565, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_BGR565, 0},

	{DRM_FORMAT_ARGB1555, 0},

	{DRM_FORMAT_ABGR1555, 0},

	{DRM_FORMAT_RGBA5551, 0},

	{DRM_FORMAT_BGRA5551, 0},

	{DRM_FORMAT_XRGB1555, 0},

	{DRM_FORMAT_XBGR1555, 0},

	{DRM_FORMAT_RGBX5551, 0},

	{DRM_FORMAT_BGRX5551, 0},

	{DRM_FORMAT_ARGB4444, 0},

	{DRM_FORMAT_ABGR4444, 0},

	{DRM_FORMAT_RGBA4444, 0},

	{DRM_FORMAT_BGRA4444, 0},

	{DRM_FORMAT_XRGB4444, 0},

	{DRM_FORMAT_XBGR4444, 0},

	{DRM_FORMAT_RGBX4444, 0},

	{DRM_FORMAT_BGRX4444, 0},

static const struct sde_format_extended plane_formats_vig[] = {

	RGB_FMTS,



	{DRM_FORMAT_NV12, 0},

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED},
@@ -84,6 +74,11 @@ static const struct sde_format_extended plane_formats_yuv[] = { 
	{DRM_FORMAT_YVYU, 0},

	{DRM_FORMAT_YUV420, 0},

	{DRM_FORMAT_YVU420, 0},



	RGB_10BIT_FMTS,

	TP10_UBWC_FMTS,

	P010_FMTS,



	{0, 0},

};
@@ -144,32 +139,13 @@ static const struct sde_format_extended wb2_formats[] = { 
	{DRM_FORMAT_NV16, 0},

	{DRM_FORMAT_YUYV, 0},



	{0, 0},

};

	RGB_10BIT_FMTS,

	TP10_UBWC_FMTS,



static const struct sde_format_extended rgb_10bit_formats[] = {

	{DRM_FORMAT_BGRA1010102, 0},

	{DRM_FORMAT_BGRX1010102, 0},

	{DRM_FORMAT_RGBA1010102, 0},

	{DRM_FORMAT_RGBX1010102, 0},

	{DRM_FORMAT_ABGR2101010, 0},

	{DRM_FORMAT_ABGR2101010, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_XBGR2101010, 0},

	{DRM_FORMAT_XBGR2101010, DRM_FORMAT_MOD_QCOM_COMPRESSED},

	{DRM_FORMAT_ARGB2101010, 0},

	{DRM_FORMAT_XRGB2101010, 0},

};



static const struct sde_format_extended p010_formats[] = {

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX},

	{0, 0},

};



static const struct sde_format_extended p010_ubwc_formats[] = {

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_DX |

		DRM_FORMAT_MOD_QCOM_COMPRESSED},

};
 


static const struct sde_format_extended tp10_ubwc_formats[] = {

	{DRM_FORMAT_NV12, DRM_FORMAT_MOD_QCOM_COMPRESSED |

		DRM_FORMAT_MOD_QCOM_DX | DRM_FORMAT_MOD_QCOM_TIGHT},

};

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+12 −8
Original line number Diff line number Diff line
@@ -800,7 +800,8 @@ static void sde_hw_sspp_setup_creq_lut(struct sde_hw_pipe *ctx, 
	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))

		return;



	if (ctx->cap && test_bit(SDE_SSPP_QOS_8LVL, &ctx->cap->features)) {

	if (ctx->cap && test_bit(SDE_PERF_SSPP_QOS_8LVL,

				&ctx->cap->perf_features)) {

		SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0 + idx, cfg->creq_lut);

		SDE_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1 + idx,

				cfg->creq_lut >> 32);
@@ -852,11 +853,13 @@ static void sde_hw_sspp_setup_ts_prefill(struct sde_hw_pipe *ctx, 
	cap = ctx->cap;



	if ((index == SDE_SSPP_RECT_SOLO || index == SDE_SSPP_RECT_0) &&

			test_bit(SDE_SSPP_TS_PREFILL, &cap->features)) {

			test_bit(SDE_PERF_SSPP_TS_PREFILL,

				&cap->perf_features)) {

		ts_offset = SSPP_TRAFFIC_SHAPER;

		ts_prefill_offset = SSPP_TRAFFIC_SHAPER_PREFILL;

	} else if (index == SDE_SSPP_RECT_1 &&

			test_bit(SDE_SSPP_TS_PREFILL_REC1, &cap->features)) {

			test_bit(SDE_PERF_SSPP_TS_PREFILL_REC1,

				&cap->perf_features)) {

		ts_offset = SSPP_TRAFFIC_SHAPER_REC1;

		ts_prefill_offset = SSPP_TRAFFIC_SHAPER_REC1_PREFILL;

	} else {
@@ -1053,7 +1056,7 @@ static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx, 
}



static void _setup_layer_ops(struct sde_hw_pipe *c,

		unsigned long features)

		unsigned long features, unsigned long perf_features)

{

	int ret;
@@ -1070,14 +1073,14 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
	if (test_bit(SDE_SSPP_EXCL_RECT, &features))

		c->ops.setup_excl_rect = _sde_hw_sspp_setup_excl_rect;



	if (test_bit(SDE_SSPP_QOS, &features)) {

	if (test_bit(SDE_PERF_SSPP_QOS, &features)) {

		c->ops.setup_danger_safe_lut =

			sde_hw_sspp_setup_danger_safe_lut;

		c->ops.setup_creq_lut = sde_hw_sspp_setup_creq_lut;

		c->ops.setup_qos_ctrl = sde_hw_sspp_setup_qos_ctrl;

	}



	if (test_bit(SDE_SSPP_TS_PREFILL, &features))

	if (test_bit(SDE_PERF_SSPP_TS_PREFILL, &perf_features))

		c->ops.setup_ts_prefill = sde_hw_sspp_setup_ts_prefill;



	if (test_bit(SDE_SSPP_CSC, &features) ||
@@ -1109,7 +1112,7 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
			c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;

	}



	if (test_bit(SDE_SSPP_CDP, &features))

	if (test_bit(SDE_PERF_SSPP_CDP, &perf_features))

		c->ops.setup_cdp = sde_hw_sspp_setup_cdp;



	_setup_layer_ops_colorproc(c, features);
@@ -1177,7 +1180,8 @@ struct sde_hw_pipe *sde_hw_sspp_init(enum sde_sspp idx, 
	hw_pipe->mdp = &catalog->mdp[0];

	hw_pipe->idx = idx;

	hw_pipe->cap = cfg;

	_setup_layer_ops(hw_pipe, hw_pipe->cap->features);

	_setup_layer_ops(hw_pipe, hw_pipe->cap->features,

		hw_pipe->cap->perf_features);



	if (hw_pipe->ops.get_scaler_ver) {

		hw_pipe->cap->sblk->scaler_blk.version =

drivers/gpu/drm/msm/sde/sde_plane.c

+3 −1
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ struct sde_plane { 


	enum sde_sspp pipe;

	uint32_t features;      /* capabilities from catalog */

	uint32_t perf_features; /* perf capabilities from catalog */

	uint32_t nformats;

	uint32_t formats[64];
@@ -264,7 +265,7 @@ static inline int _sde_plane_calc_fill_level(struct drm_plane *plane, 
	}



	psde = to_sde_plane(plane);

	if (psde->features & BIT(SDE_SSPP_QOS_FL_NOCALC))

	if (psde->perf_features & BIT(SDE_PERF_SSPP_QOS_FL_NOCALC))

		return 0;



	pstate = to_sde_plane_state(plane->state);
@@ -4096,6 +4097,7 @@ struct drm_plane *sde_plane_init(struct drm_device *dev, 


	/* cache features mask for later */

	psde->features = psde->pipe_hw->cap->features;

	psde->perf_features = psde->pipe_hw->cap->perf_features;

	psde->pipe_sblk = psde->pipe_hw->cap->sblk;

	if (!psde->pipe_sblk) {

		SDE_ERROR("[%u]invalid sblk\n", pipe);