Loading arch/arm64/kernel/traps.c +2 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #include <linux/mm_types.h> #include <asm/atomic.h> #include <asm/barrier.h> #include <asm/bug.h> #include <asm/cpufeature.h> #include <asm/daifflags.h> Loading Loading @@ -484,6 +485,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; isb(); pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); } Loading Loading
arch/arm64/kernel/traps.c +2 −0 Original line number Diff line number Diff line Loading @@ -37,6 +37,7 @@ #include <linux/mm_types.h> #include <asm/atomic.h> #include <asm/barrier.h> #include <asm/bug.h> #include <asm/cpufeature.h> #include <asm/daifflags.h> Loading Loading @@ -484,6 +485,7 @@ static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) { int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT; isb(); pt_regs_write_reg(regs, rt, arch_counter_get_cntvct()); arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); } Loading