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Commit 2d5efc19 authored by Paul Mundt's avatar Paul Mundt
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sh: pci: Move the se7751 fixups in to arch/sh/drivers/pci/. 



The se7751 was still doing the PCI fixups in its own board directory,
so we move it over to arch/sh/drivers/pci/ with the rest of the board
fixups. It has bitrotted significantly over the years, so will still
likely need a bit of work to bring back up to date.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 951a681b

arch/sh/boards/mach-se/7751/Makefile

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Original line number Diff line number Diff line
@@ -3,5 +3,3 @@ 
#



obj-y	 := setup.o io.o irq.o
 


obj-$(CONFIG_PCI) += pci.o

arch/sh/boards/mach-se/7751/pci.c

deleted100644 → 0
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Original line number Diff line number Diff line 
/*

 * linux/arch/sh/boards/se/7751/pci.c

 *

 * Author:  Ian DaSilva (idasilva@mvista.com)

 *

 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.

 *

 * May be copied or modified under the terms of the GNU General Public

 * License.  See linux/COPYING for more information.

 *

 * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)

 */



#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/init.h>

#include <linux/delay.h>

#include <linux/pci.h>



#include <asm/io.h>

#include "../../../drivers/pci/pci-sh7751.h"



#define PCIMCR_MRSET_OFF	0xBFFFFFFF

#define PCIMCR_RFSH_OFF		0xFFFFFFFB



/*

 * Only long word accesses of the PCIC's internal local registers and the

 * configuration registers from the CPU is supported.

 */

#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))

#define PCIC_READ(x) readl(PCI_REG(x))



#define xPCIBIOS_MIN_IO		board_pci_channels->io_resource->start

#define xPCIBIOS_MIN_MEM	board_pci_channels->mem_resource->start



/*

 * Description:  This function sets up and initializes the pcic, sets

 * up the BARS, maps the DRAM into the address space etc, etc.

 */

int __init pcibios_init_platform(void)

{

   unsigned long bcr1, wcr1, wcr2, wcr3, mcr;

   unsigned short bcr2;



   /*

    * Initialize the slave bus controller on the pcic.  The values used

    * here should not be hardcoded, but they should be taken from the bsc

    * on the processor, to make this function as generic as possible.

    * (i.e. Another sbc may usr different SDRAM timing settings -- in order

    * for the pcic to work, its settings need to be exactly the same.)

    */

   bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));

   bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));

   wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));

   wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));

   wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));

   mcr = (*(volatile unsigned long*)(SH7751_MCR));



   bcr1 = bcr1 | 0x00080000;  /* Enable Bit 19, BREQEN */

   (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;   



   bcr1 = bcr1 | 0x40080000;  /* Enable Bit 19 BREQEN, set PCIC to slave */

   PCIC_WRITE(SH7751_PCIBCR1, bcr1);	 /* PCIC BCR1 */

   PCIC_WRITE(SH7751_PCIBCR2, bcr2);     /* PCIC BCR2 */

   PCIC_WRITE(SH7751_PCIWCR1, wcr1);     /* PCIC WCR1 */

   PCIC_WRITE(SH7751_PCIWCR2, wcr2);     /* PCIC WCR2 */

   PCIC_WRITE(SH7751_PCIWCR3, wcr3);     /* PCIC WCR3 */

   mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;

   PCIC_WRITE(SH7751_PCIMCR, mcr);      /* PCIC MCR */





   /* Enable all interrupts, so we know what to fix */

   PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);

   PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);



   /* Set up standard PCI config registers */

   PCIC_WRITE(SH7751_PCICONF1, 	0xF39000C7); /* Bus Master, Mem & I/O access */

   PCIC_WRITE(SH7751_PCICONF2, 	0x00000000); /* PCI Class code & Revision ID */

   PCIC_WRITE(SH7751_PCICONF4, 	0xab000001); /* PCI I/O address (local regs) */

   PCIC_WRITE(SH7751_PCICONF5, 	0x0c000000); /* PCI MEM address (local RAM)  */

   PCIC_WRITE(SH7751_PCICONF6, 	0xd0000000); /* PCI MEM address (unused)     */

   PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */

   PCIC_WRITE(SH7751_PCILSR0, 0x03f00000);   /* MEM (full 64M exposed)       */

   PCIC_WRITE(SH7751_PCILSR1, 0x00000000);   /* MEM (unused)                 */

   PCIC_WRITE(SH7751_PCILAR0, 0x0c000000);   /* MEM (direct map from PCI)    */

   PCIC_WRITE(SH7751_PCILAR1, 0x00000000);   /* MEM (unused)                 */



   /* Now turn it on... */

   PCIC_WRITE(SH7751_PCICR, 0xa5000001);



   /*

    * Set PCIMBR and PCIIOBR here, assuming a single window

    * (16M MEM, 256K IO) is enough.  If a larger space is

    * needed, the readx/writex and inx/outx functions will

    * have to do more (e.g. setting registers for each call).

    */



   /*

    * Set the MBR so PCI address is one-to-one with window,

    * meaning all calls go straight through... use BUG_ON to

    * catch erroneous assumption.

    */

   BUG_ON(xPCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);



   PCIC_WRITE(SH7751_PCIMBR, xPCIBIOS_MIN_MEM);



   /* Set IOBR for window containing area specified in pci.h */

   PCIC_WRITE(SH7751_PCIIOBR, (xPCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));



   /* All done, may as well say so... */

   printk("SH7751 PCI: Finished initialization of the PCI controller\n");



   return 1;

}



int __init pcibios_map_platform_irq(u8 slot, u8 pin)

{

        switch (slot) {

        case 0: return 13;

        case 1: return 13; 	/* AMD Ethernet controller */

        case 2: return -1;

        case 3: return -1;

        case 4: return -1;

        default:

                printk("PCI: Bad IRQ mapping request for slot %d\n", slot);

                return -1;

        }

}



static struct resource sh7751_io_resource = {

	.name   = "SH7751 IO",

	.start  = SH7751_PCI_IO_BASE,

	.end    = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,

	.flags  = IORESOURCE_IO

};



static struct resource sh7751_mem_resource = {

	.name   = "SH7751 mem",

	.start  = SH7751_PCI_MEMORY_BASE,

	.end    = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,

	.flags  = IORESOURCE_MEM

};



extern struct pci_ops sh7751_pci_ops;



struct pci_channel board_pci_channels[] = {

	{ &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },

	{ NULL, NULL, NULL, 0, 0 },

};

arch/sh/drivers/pci/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o 
obj-$(CONFIG_SH_DREAMCAST)		+= ops-dreamcast.o fixups-dreamcast.o \

					   pci-dreamcast.o

obj-$(CONFIG_SH_SECUREEDGE5410)		+= fixups-snapgear.o

obj-$(CONFIG_SH_7751_SOLUTION_ENGINE)	+= fixups-se7751.o

obj-$(CONFIG_SH_RTS7751R2D)		+= fixups-rts7751r2d.o

obj-$(CONFIG_SH_SH03)			+= fixups-sh03.o

obj-$(CONFIG_SH_HIGHLANDER)		+= fixups-r7780rp.o

arch/sh/drivers/pci/fixups-se7751.c

0 → 100644
+111 −0
Original line number Diff line number Diff line 
#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/init.h>

#include <linux/delay.h>

#include <linux/pci.h>

#include <linux/io.h>

#include "pci-sh4.h"



int __init pcibios_map_platform_irq(u8 slot, u8 pin)

{

        switch (slot) {

        case 0: return 13;

        case 1: return 13;	/* AMD Ethernet controller */

        case 2: return -1;

        case 3: return -1;

        case 4: return -1;

        default:

                printk("PCI: Bad IRQ mapping request for slot %d\n", slot);

                return -1;

        }

}



#define PCIMCR_MRSET_OFF	0xBFFFFFFF

#define PCIMCR_RFSH_OFF		0xFFFFFFFB



/*

 * Only long word accesses of the PCIC's internal local registers and the

 * configuration registers from the CPU is supported.

 */

#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))

#define PCIC_READ(x) readl(PCI_REG(x))



/*

 * Description:  This function sets up and initializes the pcic, sets

 * up the BARS, maps the DRAM into the address space etc, etc.

 */

int pci_fixup_pcic(struct pci_channel *chan)

{

	unsigned long bcr1, wcr1, wcr2, wcr3, mcr;

	unsigned short bcr2;



	/*

	* Initialize the slave bus controller on the pcic.  The values used

	* here should not be hardcoded, but they should be taken from the bsc

	* on the processor, to make this function as generic as possible.

	* (i.e. Another sbc may usr different SDRAM timing settings -- in order

	* for the pcic to work, its settings need to be exactly the same.)

	*/

	bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));

	bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));

	wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));

	wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));

	wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));

	mcr = (*(volatile unsigned long*)(SH7751_MCR));



	bcr1 = bcr1 | 0x00080000;  /* Enable Bit 19, BREQEN */

	(*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;



	bcr1 = bcr1 | 0x40080000;  /* Enable Bit 19 BREQEN, set PCIC to slave */

	PCIC_WRITE(SH7751_PCIBCR1, bcr1);	 /* PCIC BCR1 */

	PCIC_WRITE(SH7751_PCIBCR2, bcr2);     /* PCIC BCR2 */

	PCIC_WRITE(SH7751_PCIWCR1, wcr1);     /* PCIC WCR1 */

	PCIC_WRITE(SH7751_PCIWCR2, wcr2);     /* PCIC WCR2 */

	PCIC_WRITE(SH7751_PCIWCR3, wcr3);     /* PCIC WCR3 */

	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;

	PCIC_WRITE(SH7751_PCIMCR, mcr);      /* PCIC MCR */





	/* Enable all interrupts, so we know what to fix */

	PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);

	PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);



	/* Set up standard PCI config registers */

	PCIC_WRITE(SH7751_PCICONF1,	0xF39000C7); /* Bus Master, Mem & I/O access */

	PCIC_WRITE(SH7751_PCICONF2,	0x00000000); /* PCI Class code & Revision ID */

	PCIC_WRITE(SH7751_PCICONF4,	0xab000001); /* PCI I/O address (local regs) */

	PCIC_WRITE(SH7751_PCICONF5,	0x0c000000); /* PCI MEM address (local RAM)  */

	PCIC_WRITE(SH7751_PCICONF6,	0xd0000000); /* PCI MEM address (unused)     */

	PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */

	PCIC_WRITE(SH7751_PCILSR0, 0x03f00000);   /* MEM (full 64M exposed)       */

	PCIC_WRITE(SH7751_PCILSR1, 0x00000000);   /* MEM (unused)                 */

	PCIC_WRITE(SH7751_PCILAR0, 0x0c000000);   /* MEM (direct map from PCI)    */

	PCIC_WRITE(SH7751_PCILAR1, 0x00000000);   /* MEM (unused)                 */



	/* Now turn it on... */

	PCIC_WRITE(SH7751_PCICR, 0xa5000001);



	/*

	* Set PCIMBR and PCIIOBR here, assuming a single window

	* (16M MEM, 256K IO) is enough.  If a larger space is

	* needed, the readx/writex and inx/outx functions will

	* have to do more (e.g. setting registers for each call).

	*/



	/*

	* Set the MBR so PCI address is one-to-one with window,

	* meaning all calls go straight through... use BUG_ON to

	* catch erroneous assumption.

	*/

	BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);



	PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);



	/* Set IOBR for window containing area specified in pci.h */

	PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));



	/* All done, may as well say so... */

	printk("SH7751 PCI: Finished initialization of the PCI controller\n");



	return 1;

}