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Commit 2d4ecc38 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: ni_mio_common: tidy up the Digital I/O subdevice init 



For aesthetics, add some whitespace to the Digital I/O subdevice init.

Only hook up the async command support if we have an irq.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 0615c162

drivers/staging/comedi/drivers/ni_mio_common.c

+24 −19
Original line number Original line Diff line number Diff line
@@ -5574,32 +5574,37 @@ static int ni_E_init(struct comedi_device *dev, 
		s->type		= COMEDI_SUBD_UNUSED;

		s->type		= COMEDI_SUBD_UNUSED;

	}

	}





	/* digital i/o subdevice */

	/* Digital I/O subdevice */



	s = &dev->subdevices[NI_DIO_SUBDEV];

	s = &dev->subdevices[NI_DIO_SUBDEV];

	s->type		= COMEDI_SUBD_DIO;

	s->type		= COMEDI_SUBD_DIO;

	s->subdev_flags	= SDF_WRITABLE | SDF_READABLE;

	s->subdev_flags	= SDF_WRITABLE | SDF_READABLE;

	s->n_chan	= board->has_32dio_chan ? 32 : 8;

	s->maxdata	= 1;

	s->maxdata	= 1;

	s->io_bits = 0;		/* all bits input */

	s->range_table	= &range_digital;

	s->range_table	= &range_digital;

	s->n_chan = board->has_32dio_chan ? 32 : 8;

	if (devpriv->is_m_series) {

	if (devpriv->is_m_series) {

		s->subdev_flags |=

		s->subdev_flags	|= SDF_LSAMPL;

		    SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */;

		s->insn_bits	= ni_m_series_dio_insn_bits;

		s->insn_bits = &ni_m_series_dio_insn_bits;

		s->insn_config	= ni_m_series_dio_insn_config;

		s->insn_config = &ni_m_series_dio_insn_config;

		if (dev->irq) {

		s->do_cmd = &ni_cdio_cmd;

			s->subdev_flags	|= SDF_CMD_WRITE /* | SDF_CMD_READ */;

		s->do_cmdtest = &ni_cdio_cmdtest;

		s->cancel = &ni_cdio_cancel;

		s->async_dma_dir = DMA_BIDIRECTIONAL;

			s->len_chanlist	= s->n_chan;

			s->len_chanlist	= s->n_chan;

			s->do_cmdtest	= ni_cdio_cmdtest;

			s->do_cmd	= ni_cdio_cmd;

			s->cancel	= ni_cdio_cancel;





			/* M-series boards use DMA */

			s->async_dma_dir = DMA_BIDIRECTIONAL;

		}



		/* reset DIO and set all channels to inputs */

		ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,

		ni_writel(dev, CDO_Reset_Bit | CDI_Reset_Bit,

			  M_Offset_CDIO_Command);

			  M_Offset_CDIO_Command);

		ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);

		ni_writel(dev, s->io_bits, M_Offset_DIO_Direction);

	} else {

	} else {

		s->insn_bits = &ni_dio_insn_bits;

		s->insn_bits	= ni_dio_insn_bits;

		s->insn_config = &ni_dio_insn_config;

		s->insn_config	= ni_dio_insn_config;



		/* set all channels to inputs */

		devpriv->dio_control = DIO_Pins_Dir(s->io_bits);

		devpriv->dio_control = DIO_Pins_Dir(s->io_bits);

		ni_writew(dev, devpriv->dio_control, DIO_Control_Register);

		ni_writew(dev, devpriv->dio_control, DIO_Control_Register);

	}

	}