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Commit 2cfe1674 authored by Jim Lin's avatar Jim Lin Committed by Mike Turquette
Browse files

clk: tegra: Enable hardware control of PLLE 



Enable hardware control of PLLE spread-spectrum, IDDQ, and enable
controls when enabling PLLE.  The hardware (e.g. XUSB) using PLLE
will use these controls for power-saving optimizations.

Signed-off-by: default avatarJim Lin <jilin@nvidia.com>
Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent c675a00c

drivers/clk/tegra/clk-pll.c

+32 −1
Original line number Diff line number Diff line
@@ -96,10 +96,20 @@ 
	(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)



#define PLLE_AUX_PLLP_SEL	BIT(2)

#define PLLE_AUX_USE_LOCKDET	BIT(3)

#define PLLE_AUX_ENABLE_SWCTL	BIT(4)

#define PLLE_AUX_SS_SWCTL	BIT(6)

#define PLLE_AUX_SEQ_ENABLE	BIT(24)

#define PLLE_AUX_SEQ_START_STATE BIT(25)

#define PLLE_AUX_PLLRE_SEL	BIT(28)



#define XUSBIO_PLL_CFG0		0x51c

#define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL	BIT(0)

#define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL	BIT(2)

#define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET	BIT(6)

#define XUSBIO_PLL_CFG0_SEQ_ENABLE		BIT(24)

#define XUSBIO_PLL_CFG0_SEQ_START_STATE		BIT(25)



#define PLLE_MISC_PLLE_PTS	BIT(8)

#define PLLE_MISC_IDDQ_SW_VALUE	BIT(13)

#define PLLE_MISC_IDDQ_SW_CTRL	BIT(14)
@@ -1318,7 +1328,28 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	pll_writel(val, PLLE_SS_CTRL, pll);

	udelay(1);



	/* TODO: enable hw control of xusb brick pll */

	/* Enable hw control of xusb brick pll */

	val = pll_readl_misc(pll);

	val &= ~PLLE_MISC_IDDQ_SW_CTRL;

	pll_writel_misc(val, pll);



	val = pll_readl(pll->params->aux_reg, pll);

	val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);

	val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);

	pll_writel(val, pll->params->aux_reg, pll);

	udelay(1);

	val |= PLLE_AUX_SEQ_ENABLE;

	pll_writel(val, pll->params->aux_reg, pll);



	val = pll_readl(XUSBIO_PLL_CFG0, pll);

	val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |

		XUSBIO_PLL_CFG0_SEQ_START_STATE);

	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |

		 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);

	pll_writel(val, XUSBIO_PLL_CFG0, pll);

	udelay(1);

	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;

	pll_writel(val, XUSBIO_PLL_CFG0, pll);



out:

	if (pll->lock)