Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2cb3a34a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2017-10-18-1' of... 

Merge tag 'drm-intel-fixes-2017-10-18-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

Fix for stable:

- Fix DDI translation tables for BDW (Chris).

Critical fix:

- Fix GPU Hang on GVT (Changbin).

Other fixes:

- Fix eviction when GGTT is idle (Chris).
- CNL PLL fixes (Rodrigo).
- Fix pwrite into shmemfs (Chris).
- Mask bits for BXT and CHV L3 Workaround
  WaProgramL3SqcReg1Default (Oscar).

* tag 'drm-intel-fixes-2017-10-18-1' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Use a mask when applying WaProgramL3SqcReg1Default
  drm/i915: Report -EFAULT before pwrite fast path into shmemfs
  drm/i915/cnl: Fix PLL initialization for HDMI.
  drm/i915/cnl: Fix PLL mapping.
  drm/i915: Use bdw_ddi_translations_fdi for Broadwell
  drm/i915: Fix eviction when the GGTT is idle but full
  drm/i915/gvt: Fix GPU hang after reusing vGPU instance across different guest OS
parents 3eea56cc dd00ed9e

drivers/gpu/drm/i915/gvt/sched_policy.c

+10 −12
Original line number Diff line number Diff line
@@ -308,20 +308,8 @@ static int tbs_sched_init_vgpu(struct intel_vgpu *vgpu) 


static void tbs_sched_clean_vgpu(struct intel_vgpu *vgpu)

{

	struct intel_gvt_workload_scheduler *scheduler = &vgpu->gvt->scheduler;

	int ring_id;



	kfree(vgpu->sched_data);

	vgpu->sched_data = NULL;



	spin_lock_bh(&scheduler->mmio_context_lock);

	for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {

		if (scheduler->engine_owner[ring_id] == vgpu) {

			intel_gvt_switch_mmio(vgpu, NULL, ring_id);

			scheduler->engine_owner[ring_id] = NULL;

		}

	}

	spin_unlock_bh(&scheduler->mmio_context_lock);

}



static void tbs_sched_start_schedule(struct intel_vgpu *vgpu)
@@ -388,6 +376,7 @@ void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu) 
{

	struct intel_gvt_workload_scheduler *scheduler =

		&vgpu->gvt->scheduler;

	int ring_id;



	gvt_dbg_core("vgpu%d: stop schedule\n", vgpu->id);
@@ -401,4 +390,13 @@ void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu) 
		scheduler->need_reschedule = true;

		scheduler->current_vgpu = NULL;

	}



	spin_lock_bh(&scheduler->mmio_context_lock);

	for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {

		if (scheduler->engine_owner[ring_id] == vgpu) {

			intel_gvt_switch_mmio(vgpu, NULL, ring_id);

			scheduler->engine_owner[ring_id] = NULL;

		}

	}

	spin_unlock_bh(&scheduler->mmio_context_lock);

}

drivers/gpu/drm/i915/i915_gem.c

+3 −0
Original line number Diff line number Diff line
@@ -2657,6 +2657,9 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, 
	if (READ_ONCE(obj->mm.pages))

		return -ENODEV;



	if (obj->mm.madv != I915_MADV_WILLNEED)

		return -EFAULT;



	/* Before the pages are instantiated the object is treated as being

	 * in the CPU domain. The pages will be clflushed as required before

	 * use, and we can freely write into the pages directly. If userspace

drivers/gpu/drm/i915/i915_gem_evict.c

+39 −24
Original line number Diff line number Diff line
@@ -33,17 +33,16 @@ 
#include "intel_drv.h"

#include "i915_trace.h"



static bool ggtt_is_idle(struct drm_i915_private *dev_priv)

static bool ggtt_is_idle(struct drm_i915_private *i915)

{

	struct i915_ggtt *ggtt = &dev_priv->ggtt;

       struct intel_engine_cs *engine;

       enum intel_engine_id id;



	for_each_engine(engine, dev_priv, id) {

		struct intel_timeline *tl;

       if (i915->gt.active_requests)

	       return false;



		tl = &ggtt->base.timeline.engine[engine->id];

		if (i915_gem_active_isset(&tl->last_request))

       for_each_engine(engine, i915, id) {

	       if (engine->last_retired_context != i915->kernel_context)

		       return false;

       }
@@ -157,7 +156,8 @@ i915_gem_evict_something(struct i915_address_space *vm, 
				    min_size, alignment, cache_level,

				    start, end, mode);



	/* Retire before we search the active list. Although we have

	/*

	 * Retire before we search the active list. Although we have

	 * reasonable accuracy in our retirement lists, we may have

	 * a stray pin (preventing eviction) that can only be resolved by

	 * retiring.
@@ -182,7 +182,8 @@ i915_gem_evict_something(struct i915_address_space *vm, 
		BUG_ON(ret);

	}



	/* Can we unpin some objects such as idle hw contents,

	/*

	 * Can we unpin some objects such as idle hw contents,

	 * or pending flips? But since only the GGTT has global entries

	 * such as scanouts, rinbuffers and contexts, we can skip the

	 * purge when inspecting per-process local address spaces.
@@ -190,19 +191,33 @@ i915_gem_evict_something(struct i915_address_space *vm, 
	if (!i915_is_ggtt(vm) || flags & PIN_NONBLOCK)

		return -ENOSPC;



	if (ggtt_is_idle(dev_priv)) {

		/* If we still have pending pageflip completions, drop

		 * back to userspace to give our workqueues time to

		 * acquire our locks and unpin the old scanouts.

	/*

	 * Not everything in the GGTT is tracked via VMA using

	 * i915_vma_move_to_active(), otherwise we could evict as required

	 * with minimal stalling. Instead we are forced to idle the GPU and

	 * explicitly retire outstanding requests which will then remove

	 * the pinning for active objects such as contexts and ring,

	 * enabling us to evict them on the next iteration.

	 *

	 * To ensure that all user contexts are evictable, we perform

	 * a switch to the perma-pinned kernel context. This all also gives

	 * us a termination condition, when the last retired context is

	 * the kernel's there is no more we can evict.

	 */

		return intel_has_pending_fb_unpin(dev_priv) ? -EAGAIN : -ENOSPC;

	}



	if (!ggtt_is_idle(dev_priv)) {

		ret = ggtt_flush(dev_priv);

		if (ret)

			return ret;



		goto search_again;

	}



	/*

	 * If we still have pending pageflip completions, drop

	 * back to userspace to give our workqueues time to

	 * acquire our locks and unpin the old scanouts.

	 */

	return intel_has_pending_fb_unpin(dev_priv) ? -EAGAIN : -ENOSPC;



found:

	/* drm_mm doesn't allow any other other operations while

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -6998,6 +6998,7 @@ enum { 
 */

#define  L3_GENERAL_PRIO_CREDITS(x)		(((x) >> 1) << 19)

#define  L3_HIGH_PRIO_CREDITS(x)		(((x) >> 1) << 14)

#define  L3_PRIO_CREDITS_MASK			((0x1f << 19) | (0x1f << 14))



#define GEN7_L3CNTLREG1				_MMIO(0xB01C)

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C

drivers/gpu/drm/i915/intel_ddi.c

+3 −4
Original line number Diff line number Diff line
@@ -664,8 +664,8 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, 
			    int *n_entries)

{

	if (IS_BROADWELL(dev_priv)) {

		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);

		return hsw_ddi_translations_fdi;

		*n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);

		return bdw_ddi_translations_fdi;

	} else if (IS_HASWELL(dev_priv)) {

		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);

		return hsw_ddi_translations_fdi;
@@ -2102,8 +2102,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, 
		 * register writes.

		 */

		val = I915_READ(DPCLKA_CFGCR0);

		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |

			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));

		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);

		I915_WRITE(DPCLKA_CFGCR0, val);

	} else if (IS_GEN9_BC(dev_priv)) {

		/* DDI -> PLL mapping  */