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Commit 2c0b6871 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge branch 'next-samsung-clkdev-fix' into next-samsung-devel

parents 2d21237e e4805599

arch/arm/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -682,6 +682,7 @@ config ARCH_S3C2410 
	select GENERIC_GPIO

	select ARCH_HAS_CPUFREQ

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARCH_USES_GETTIMEOFFSET

	select HAVE_S3C2410_I2C if I2C

	help
@@ -699,6 +700,7 @@ config ARCH_S3C64XX 
	select CPU_V6

	select ARM_VIC

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select NO_IOPORT

	select ARCH_USES_GETTIMEOFFSET

	select ARCH_HAS_CPUFREQ
@@ -723,6 +725,7 @@ config ARCH_S5P64X0 
	select CPU_V6

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select GENERIC_CLOCKEVENTS

	select HAVE_SCHED_CLOCK
@@ -736,6 +739,7 @@ config ARCH_S5PC100 
	bool "Samsung S5PC100"

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select CPU_V7

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_USES_GETTIMEOFFSET
@@ -751,6 +755,7 @@ config ARCH_S5PV210 
	select ARCH_SPARSEMEM_ENABLE

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS
@@ -767,6 +772,7 @@ config ARCH_EXYNOS4 
	select ARCH_SPARSEMEM_ENABLE

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS

	select HAVE_S3C_RTC if RTC_CLASS

arch/arm/mach-exynos4/clock.c

+57 −120
Original line number Diff line number Diff line
@@ -27,24 +27,20 @@ 


static struct clk clk_sclk_hdmi27m = {

	.name		= "sclk_hdmi27m",

	.id		= -1,

	.rate		= 27000000,

};



static struct clk clk_sclk_hdmiphy = {

	.name		= "sclk_hdmiphy",

	.id		= -1,

};



static struct clk clk_sclk_usbphy0 = {

	.name		= "sclk_usbphy0",

	.id		= -1,

	.rate		= 27000000,

};



static struct clk clk_sclk_usbphy1 = {

	.name		= "sclk_usbphy1",

	.id		= -1,

};



static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) 
static struct clksrc_clk clk_mout_apll = {

	.clk	= {

		.name		= "mout_apll",

		.id		= -1,

	},

	.sources	= &clk_src_apll,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = { 
static struct clksrc_clk clk_sclk_apll = {

	.clk	= {

		.name		= "sclk_apll",

		.id		= -1,

		.parent		= &clk_mout_apll.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = { 
static struct clksrc_clk clk_mout_epll = {

	.clk	= {

		.name		= "mout_epll",

		.id		= -1,

	},

	.sources	= &clk_src_epll,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = { 
static struct clksrc_clk clk_mout_mpll = {

	.clk = {

		.name		= "mout_mpll",

		.id		= -1,

	},

	.sources	= &clk_src_mpll,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = { 
static struct clksrc_clk clk_moutcore = {

	.clk	= {

		.name		= "moutcore",

		.id		= -1,

	},

	.sources	= &clkset_moutcore,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = { 
static struct clksrc_clk clk_coreclk = {

	.clk	= {

		.name		= "core_clk",

		.id		= -1,

		.parent		= &clk_moutcore.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = { 
static struct clksrc_clk clk_armclk = {

	.clk	= {

		.name		= "armclk",

		.id		= -1,

		.parent		= &clk_coreclk.clk,

	},

};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = { 
static struct clksrc_clk clk_aclk_corem0 = {

	.clk	= {

		.name		= "aclk_corem0",

		.id		= -1,

		.parent		= &clk_coreclk.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = { 
static struct clksrc_clk clk_aclk_cores = {

	.clk	= {

		.name		= "aclk_cores",

		.id		= -1,

		.parent		= &clk_coreclk.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = { 
static struct clksrc_clk clk_aclk_corem1 = {

	.clk	= {

		.name		= "aclk_corem1",

		.id		= -1,

		.parent		= &clk_coreclk.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = { 
static struct clksrc_clk clk_periphclk = {

	.clk	= {

		.name		= "periphclk",

		.id		= -1,

		.parent		= &clk_coreclk.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = { 
static struct clksrc_clk clk_mout_corebus = {

	.clk	= {

		.name		= "mout_corebus",

		.id		= -1,

	},

	.sources	= &clkset_mout_corebus,

	.reg_src	= { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = { 
static struct clksrc_clk clk_sclk_dmc = {

	.clk	= {

		.name		= "sclk_dmc",

		.id		= -1,

		.parent		= &clk_mout_corebus.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = { 
static struct clksrc_clk clk_aclk_cored = {

	.clk	= {

		.name		= "aclk_cored",

		.id		= -1,

		.parent		= &clk_sclk_dmc.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = { 
static struct clksrc_clk clk_aclk_corep = {

	.clk	= {

		.name		= "aclk_corep",

		.id		= -1,

		.parent		= &clk_aclk_cored.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = { 
static struct clksrc_clk clk_aclk_acp = {

	.clk	= {

		.name		= "aclk_acp",

		.id		= -1,

		.parent		= &clk_mout_corebus.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = { 
static struct clksrc_clk clk_pclk_acp = {

	.clk	= {

		.name		= "pclk_acp",

		.id		= -1,

		.parent		= &clk_aclk_acp.clk,

	},

	.reg_div	= { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = { 
static struct clksrc_clk clk_aclk_200 = {

	.clk	= {

		.name		= "aclk_200",

		.id		= -1,

	},

	.sources	= &clkset_aclk,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = { 
static struct clksrc_clk clk_aclk_100 = {

	.clk	= {

		.name		= "aclk_100",

		.id		= -1,

	},

	.sources	= &clkset_aclk,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = { 
static struct clksrc_clk clk_aclk_160 = {

	.clk	= {

		.name		= "aclk_160",

		.id		= -1,

	},

	.sources	= &clkset_aclk,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = { 
static struct clksrc_clk clk_aclk_133 = {

	.clk	= {

		.name		= "aclk_133",

		.id		= -1,

	},

	.sources	= &clkset_aclk,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = { 
static struct clksrc_clk clk_vpllsrc = {

	.clk	= {

		.name		= "vpll_src",

		.id		= -1,

		.enable		= exynos4_clksrc_mask_top_ctrl,

		.ctrlbit	= (1 << 0),

	},
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = { 
static struct clksrc_clk clk_sclk_vpll = {

	.clk	= {

		.name		= "sclk_vpll",

		.id		= -1,

	},

	.sources	= &clkset_sclk_vpll,

	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = { 
static struct clk init_clocks_off[] = {

	{

		.name		= "timers",

		.id		= -1,

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1<<24),

	}, {

		.name		= "csis",

		.id		= 0,

		.devname	= "s5p-mipi-csis.0",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "csis",

		.id		= 1,

		.devname	= "s5p-mipi-csis.1",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 5),

	}, {

		.name		= "fimc",

		.id		= 0,

		.devname	= "exynos4-fimc.0",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "fimc",

		.id		= 1,

		.devname	= "exynos4-fimc.1",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "fimc",

		.id		= 2,

		.devname	= "exynos4-fimc.2",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 2),

	}, {

		.name		= "fimc",

		.id		= 3,

		.devname	= "exynos4-fimc.3",

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "fimd",

		.id		= 0,

		.devname	= "s5pv310-fb.0",

		.enable		= exynos4_clk_ip_lcd0_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "fimd",

		.id		= 1,

		.devname	= "s5pv310-fb.1",

		.enable		= exynos4_clk_ip_lcd1_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "sataphy",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "hsmmc",

		.id		= 0,

		.devname	= "s3c-sdhci.0",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 5),

	}, {

		.name		= "hsmmc",

		.id		= 1,

		.devname	= "s3c-sdhci.1",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 6),

	}, {

		.name		= "hsmmc",

		.id		= 2,

		.devname	= "s3c-sdhci.2",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 7),

	}, {

		.name		= "hsmmc",

		.id		= 3,

		.devname	= "s3c-sdhci.3",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 8),

	}, {

		.name		= "hsmmc",

		.id		= 4,

		.name		= "dwmmc",

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 9),

	}, {

		.name		= "sata",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

	}, {

		.name		= "pdma",

		.id		= 0,

		.devname	= "s3c-pl330.0",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "pdma",

		.id		= 1,

		.devname	= "s3c-pl330.1",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "adc",

		.id		= -1,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 15),

	}, {

		.name		= "keypad",

		.id		= -1,

		.enable		= exynos4_clk_ip_perir_ctrl,

		.ctrlbit	= (1 << 16),

	}, {

		.name		= "rtc",

		.id		= -1,

		.enable		= exynos4_clk_ip_perir_ctrl,

		.ctrlbit	= (1 << 15),

	}, {

		.name		= "watchdog",

		.id		= -1,

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_perir_ctrl,

		.ctrlbit	= (1 << 14),

	}, {

		.name		= "usbhost",

		.id		= -1,

		.enable		= exynos4_clk_ip_fsys_ctrl ,

		.ctrlbit	= (1 << 12),

	}, {

		.name		= "otg",

		.id		= -1,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 13),

	}, {

		.name		= "spi",

		.id		= 0,

		.devname	= "s3c64xx-spi.0",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 16),

	}, {

		.name		= "spi",

		.id		= 1,

		.devname	= "s3c64xx-spi.1",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 17),

	}, {

		.name		= "spi",

		.id		= 2,

		.devname	= "s3c64xx-spi.2",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 18),

	}, {

		.name		= "iis",

		.id		= 0,

		.devname	= "samsung-i2s.0",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 19),

	}, {

		.name		= "iis",

		.id		= 1,

		.devname	= "samsung-i2s.1",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 20),

	}, {

		.name		= "iis",

		.id		= 2,

		.devname	= "samsung-i2s.2",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 21),

	}, {
@@ -562,125 +525,110 @@ static struct clk init_clocks_off[] = { 
		.ctrlbit	= (1 << 27),

	}, {

		.name		= "fimg2d",

		.id		= -1,

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "i2c",

		.id		= 0,

		.devname	= "s3c2440-i2c.0",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 6),

	}, {

		.name		= "i2c",

		.id		= 1,

		.devname	= "s3c2440-i2c.1",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 7),

	}, {

		.name		= "i2c",

		.id		= 2,

		.devname	= "s3c2440-i2c.2",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 8),

	}, {

		.name		= "i2c",

		.id		= 3,

		.devname	= "s3c2440-i2c.3",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 9),

	}, {

		.name		= "i2c",

		.id		= 4,

		.devname	= "s3c2440-i2c.4",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 10),

	}, {

		.name		= "i2c",

		.id		= 5,

		.devname	= "s3c2440-i2c.5",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 11),

	}, {

		.name		= "i2c",

		.id		= 6,

		.devname	= "s3c2440-i2c.6",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 12),

	}, {

		.name		= "i2c",

		.id		= 7,

		.devname	= "s3c2440-i2c.7",

		.parent		= &clk_aclk_100.clk,

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 13),

	}, {

		.name		= "SYSMMU_MDMA",

		.id		= -1,

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 5),

	}, {

		.name		= "SYSMMU_FIMC0",

		.id		= -1,

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 7),

	}, {

		.name		= "SYSMMU_FIMC1",

		.id		= -1,

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 8),

	}, {

		.name		= "SYSMMU_FIMC2",

		.id		= -1,

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 9),

	}, {

		.name		= "SYSMMU_FIMC3",

		.id		= -1,

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 10),

	}, {

		.name		= "SYSMMU_JPEG",

		.id		= -1,

		.enable		= exynos4_clk_ip_cam_ctrl,

		.ctrlbit	= (1 << 11),

	}, {

		.name		= "SYSMMU_FIMD0",

		.id		= -1,

		.enable		= exynos4_clk_ip_lcd0_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "SYSMMU_FIMD1",

		.id		= -1,

		.enable		= exynos4_clk_ip_lcd1_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "SYSMMU_PCIe",

		.id		= -1,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 18),

	}, {

		.name		= "SYSMMU_G2D",

		.id		= -1,

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "SYSMMU_ROTATOR",

		.id		= -1,

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "SYSMMU_TV",

		.id		= -1,

		.enable		= exynos4_clk_ip_tv_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "SYSMMU_MFC_L",

		.id		= -1,

		.enable		= exynos4_clk_ip_mfc_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "SYSMMU_MFC_R",

		.id		= -1,

		.enable		= exynos4_clk_ip_mfc_ctrl,

		.ctrlbit	= (1 << 2),

	}
@@ -689,32 +637,32 @@ static struct clk init_clocks_off[] = { 
static struct clk init_clocks[] = {

	{

		.name		= "uart",

		.id		= 0,

		.devname	= "s5pv210-uart.0",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "uart",

		.id		= 1,

		.devname	= "s5pv210-uart.1",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 1),

	}, {

		.name		= "uart",

		.id		= 2,

		.devname	= "s5pv210-uart.2",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 2),

	}, {

		.name		= "uart",

		.id		= 3,

		.devname	= "s5pv210-uart.3",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "uart",

		.id		= 4,

		.devname	= "s5pv210-uart.4",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "uart",

		.id		= 5,

		.devname	= "s5pv210-uart.5",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 5),

	}
@@ -750,7 +698,6 @@ static struct clksrc_sources clkset_mout_g2d0 = { 
static struct clksrc_clk clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

		.id		= -1,

	},

	.sources	= &clkset_mout_g2d0,

	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +716,6 @@ static struct clksrc_sources clkset_mout_g2d1 = { 
static struct clksrc_clk clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

		.id		= -1,

	},

	.sources	= &clkset_mout_g2d1,

	.reg_src	= { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -788,7 +734,6 @@ static struct clksrc_sources clkset_mout_g2d = { 
static struct clksrc_clk clk_dout_mmc0 = {

	.clk		= {

		.name		= "dout_mmc0",

		.id		= -1,

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +743,6 @@ static struct clksrc_clk clk_dout_mmc0 = { 
static struct clksrc_clk clk_dout_mmc1 = {

	.clk		= {

		.name		= "dout_mmc1",

		.id		= -1,

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +752,6 @@ static struct clksrc_clk clk_dout_mmc1 = { 
static struct clksrc_clk clk_dout_mmc2 = {

	.clk		= {

		.name		= "dout_mmc2",

		.id		= -1,

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +761,6 @@ static struct clksrc_clk clk_dout_mmc2 = { 
static struct clksrc_clk clk_dout_mmc3 = {

	.clk		= {

		.name		= "dout_mmc3",

		.id		= -1,

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +770,6 @@ static struct clksrc_clk clk_dout_mmc3 = { 
static struct clksrc_clk clk_dout_mmc4 = {

	.clk		= {

		.name		= "dout_mmc4",

		.id		= -1,

	},

	.sources = &clkset_group,

	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +780,7 @@ static struct clksrc_clk clksrcs[] = { 
	{

		.clk	= {

			.name		= "uclk1",

			.id		= 0,

			.devname	= "s5pv210-uart.0",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 0),

		},
@@ -849,7 +790,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "uclk1",

			.id		= 1,

			.devname	= "s5pv210-uart.1",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 4),

		},
@@ -859,7 +800,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "uclk1",

			.id		= 2,

			.devname	= "s5pv210-uart.2",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 8),

		},
@@ -869,7 +810,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "uclk1",

			.id		= 3,

			.devname	= "s5pv210-uart.3",

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 12),

		},
@@ -879,7 +820,6 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_pwm",

			.id		= -1,

			.enable		= exynos4_clksrc_mask_peril0_ctrl,

			.ctrlbit	= (1 << 24),

		},
@@ -889,7 +829,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_csis",

			.id		= 0,

			.devname	= "s5p-mipi-csis.0",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 24),

		},
@@ -899,7 +839,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_csis",

			.id		= 1,

			.devname	= "s5p-mipi-csis.1",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 28),

		},
@@ -909,7 +849,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_cam",

			.id		= 0,

			.devname	= "exynos4-fimc.0",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 16),

		},
@@ -919,7 +859,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_cam",

			.id		= 1,

			.devname	= "exynos4-fimc.1",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 20),

		},
@@ -929,7 +869,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimc",

			.id		= 0,

			.devname	= "exynos4-fimc.0",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 0),

		},
@@ -939,7 +879,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimc",

			.id		= 1,

			.devname	= "exynos4-fimc.1",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 4),

		},
@@ -949,7 +889,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimc",

			.id		= 2,

			.devname	= "exynos4-fimc.2",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 8),

		},
@@ -959,7 +899,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimc",

			.id		= 3,

			.devname	= "exynos4-fimc.3",

			.enable		= exynos4_clksrc_mask_cam_ctrl,

			.ctrlbit	= (1 << 12),

		},
@@ -969,7 +909,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimd",

			.id		= 0,

			.devname	= "s5pv310-fb.0",

			.enable		= exynos4_clksrc_mask_lcd0_ctrl,

			.ctrlbit	= (1 << 0),

		},
@@ -979,7 +919,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimd",

			.id		= 1,

			.devname	= "s5pv310-fb.1",

			.enable		= exynos4_clksrc_mask_lcd1_ctrl,

			.ctrlbit	= (1 << 0),

		},
@@ -989,7 +929,6 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_sata",

			.id		= -1,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 24),

		},
@@ -999,7 +938,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_spi",

			.id		= 0,

			.devname	= "s3c64xx-spi.0",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 16),

		},
@@ -1009,7 +948,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_spi",

			.id		= 1,

			.devname	= "s3c64xx-spi.1",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 20),

		},
@@ -1019,7 +958,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_spi",

			.id		= 2,

			.devname	= "s3c64xx-spi.2",

			.enable		= exynos4_clksrc_mask_peril1_ctrl,

			.ctrlbit	= (1 << 24),

		},
@@ -1029,7 +968,6 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_fimg2d",

			.id		= -1,

		},

		.sources = &clkset_mout_g2d,

		.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
@@ -1037,7 +975,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.id		= 0,

			.devname	= "s3c-sdhci.0",

			.parent		= &clk_dout_mmc0.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 0),
@@ -1046,7 +984,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.id		= 1,

			.devname	= "s3c-sdhci.1",

			.parent         = &clk_dout_mmc1.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 4),
@@ -1055,7 +993,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.id		= 2,

			.devname	= "s3c-sdhci.2",

			.parent         = &clk_dout_mmc2.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 8),
@@ -1064,7 +1002,7 @@ static struct clksrc_clk clksrcs[] = { 
	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.id		= 3,

			.devname	= "s3c-sdhci.3",

			.parent         = &clk_dout_mmc3.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 12),
@@ -1072,8 +1010,7 @@ static struct clksrc_clk clksrcs[] = { 
		.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },

	}, {

		.clk		= {

			.name		= "sclk_mmc",

			.id		= 4,

			.name		= "sclk_dwmmc",

			.parent         = &clk_dout_mmc4.clk,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 16),

arch/arm/mach-exynos4/include/mach/clkdev.h

0 → 100644
+7 −0
Original line number Diff line number Diff line 
#ifndef __MACH_CLKDEV_H__

#define __MACH_CLKDEV_H__



#define __clk_get(clk) ({ 1; })

#define __clk_put(clk) do {} while (0)



#endif

arch/arm/mach-s3c2412/clock.c

+3 −33
Original line number Diff line number Diff line
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) 


static struct clk clk_erefclk = {

	.name		= "erefclk",

	.id		= -1,

};



static struct clk clk_urefclk = {

	.name		= "urefclk",

	.id		= -1,

};



static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) 


static struct clk clk_usysclk = {

	.name		= "usysclk",

	.id		= -1,

	.parent		= &clk_xtal,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = { 
static struct clk clk_mrefclk = {

	.name		= "mrefclk",

	.parent		= &clk_xtal,

	.id		= -1,

};



static struct clk clk_mdivclk = {

	.name		= "mdivclk",

	.parent		= &clk_xtal,

	.id		= -1,

};



static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) 


static struct clk clk_usbsrc = {

	.name		= "usbsrc",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_usbsrc,

		.set_rate	= s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) 


static struct clk clk_msysclk = {

	.name		= "msysclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_msysclk,

	},
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) 


static struct clk clk_armclk = {

	.name		= "armclk",

	.id		= -1,

	.parent		= &clk_msysclk,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) 


static struct clk clk_uart = {

	.name		= "uartclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_uart,

		.set_rate	= s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) 


static struct clk clk_i2s = {

	.name		= "i2sclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_i2s,

		.set_rate	= s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) 


static struct clk clk_cam = {

	.name		= "camif-upll",	/* same as 2440 name */

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_cam,

		.set_rate	= s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = { 
static struct clk init_clocks_disable[] = {

	{

		.name		= "nand",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_NAND,

	}, {

		.name		= "sdi",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_SDI,

	}, {

		.name		= "adc",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_ADC,

	}, {

		.name		= "i2c",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_IIC,

	}, {

		.name		= "iis",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_IIS,

	}, {

		.name		= "spi",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { 
static struct clk init_clocks[] = {

	{

		.name		= "dma",

		.id		= 0,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA0,

	}, {

		.name		= "dma",

		.id		= 1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA1,

	}, {

		.name		= "dma",

		.id		= 2,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA2,

	}, {

		.name		= "dma",

		.id		= 3,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA3,

	}, {

		.name		= "lcd",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_LCDC,

	}, {

		.name		= "gpio",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_GPIO,

	}, {

		.name		= "usb-host",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USBH,

	}, {

		.name		= "usb-device",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USBD,

	}, {

		.name		= "timers",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_PWMT,

	}, {

		.name		= "uart",

		.id		= 0,

		.devname	= "s3c2412-uart.0",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART0,

	}, {

		.name		= "uart",

		.id		= 1,

		.devname	= "s3c2412-uart.1",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART1,

	}, {

		.name		= "uart",

		.id		= 2,

		.devname	= "s3c2412-uart.2",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART2,

	}, {

		.name		= "rtc",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_RTC,

	}, {

		.name		= "watchdog",

		.id		= -1,

		.parent		= &clk_p,

		.ctrlbit	= 0,

	}, {

		.name		= "usb-bus-gadget",

		.id		= -1,

		.parent		= &clk_usb_bus,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USB_DEV48,

	}, {

		.name		= "usb-bus-host",

		.id		= -1,

		.parent		= &clk_usb_bus,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USB_HOST48,

arch/arm/mach-s3c2416/clock.c

+5 −5
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { 
	[0] = {

		.clk = {

			.name	= "hsmmc-div",

			.id	= 0,

			.devname	= "s3c-sdhci.0",

			.parent	= &clk_esysclk.clk,

		},

		.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { 
	[1] = {

		.clk = {

			.name	= "hsmmc-div",

			.id	= 1,

			.devname	= "s3c-sdhci.1",

			.parent	= &clk_esysclk.clk,

		},

		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = { 
static struct clksrc_clk hsmmc_mux[] = {

	[0] = {

		.clk	= {

			.id	= 0,

			.name	= "hsmmc-if",

			.devname	= "s3c-sdhci.0",

			.ctrlbit = (1 << 6),

			.enable = s3c2443_clkcon_enable_s,

		},
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { 
	},

	[1] = {

		.clk	= {

			.id	= 1,

			.name	= "hsmmc-if",

			.devname	= "s3c-sdhci.1",

			.ctrlbit = (1 << 12),

			.enable = s3c2443_clkcon_enable_s,

		},
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = { 


static struct clk hsmmc0_clk = {

	.name		= "hsmmc",

	.id		= 0,

	.devname	= "s3c-sdhci.0",

	.parent		= &clk_h,

	.enable		= s3c2443_clkcon_enable_h,

	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,